MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I
2
C,
10-Bit ADCs in Ultra-Small Packages
7
Maxim Integrated
0.9990
0.9994
0.9992
0.9998
0.9996
1.0002
1.0000
1.0004
1.0008
1.0006
1.0010
-40 -10 5-25 20 35 50 65 80
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX11606 toc09
TEMPERATURE (°C)
V
REF
NORMALIZED
MAX11610/MAX11608/MAX11606
MAX11611/MAX11609/MAX11607
NORMALIZED TO REFERENCE VALUE
T
A
= +25°C
0.99990
0.99994
0.99992
0.99998
0.99996
1.00002
1.00000
1.00004
1.00008
1.00006
1.00010
2.7 3.3 3.6 3.93.0 4.2 4.5 4.8 5.1 5.4
NORMALIZED REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX11606 toc10
V
DD
(V)
V
REF
NORMALIZED
MAX11610/11608/MAX11606,
NORMALIZED TO
REFERENCE VALUE AT
V
DD
= 5V
MAX11611/11609/MAX11607,
NORMALIZED TO
REFERENCE VALUE AT
V
DD
= 3.3V
Typical Operating Characteristics (continued)
(V
DD
= 3.3V (MAX11607/MAX11609/MAX11611), V
DD
= 5V (MAX11606/MAX11608/MAX11610), f
SCL
= 1.7MHz, external clock,
f
SAMPLE
= 94.4ksps, single-ended, unipolar, T
A
= +25°C, unless otherwise noted.)
-1.0
-0.8
-0.9
-0.6
-0.7
-0.4
-0.5
-0.3
-0.1
-0.2
0
-40 -10 5-25 2035506580
OFFSET ERROR vs. TEMPERATURE
MAX11606 toc11
TEMPERATURE (°C)
OFFSET ERROR (LSB)
-1.0
-0.8
-0.9
-0.6
-0.7
-0.4
-0.5
-0.3
-0.1
-0.2
0
2.7 3.3 3.6 3.93.0 4.2 4.5 4.8 5.1 5.4
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX11606 toc12
V
DD
(V)
OFFSET ERROR (LSB)
0
0.2
0.1
0.4
0.3
0.6
0.5
0.7
0.9
0.8
1.0
-40 -10 5-25 2035506580
GAIN ERROR vs. TEMPERATURE
MAX11606 toc13
TEMPERATURE (°C)
GAIN ERROR (LSB)
0
0.3
0.2
0.1
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2.7 3.73.2 4.2 4.7 5.2
GAIN ERROR vs. SUPPLY VOLTAGE
MAX11606 toc14
V
DD
(V)
GAIN ERROR (LSB)
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I
2
C,
10-Bit ADCs in Ultra-Small Packages
8
Maxim Integrated
Pin Description
PIN
MAX11606
MAX11607
MAX11607
MAX11608
MAX11609
MAX11610
MAX11611
µMAX WLP QSOP
NAME FUNCTION
1, 2, 3 A1, A2, A3 5, 6, 7 5, 6, 7 AIN0, AIN1, AIN2
8–12 8–12 AIN3–AIN7
4, 3, 2 AIN8, AIN9, AIN10
Analog Inputs
4 A4 AIN3/REF
Analog Input 3/Reference Input or Output. Selected in
the setup register (see Tables 1 and 6).
1 REF
Reference Input or Output. Selected in the setup
register (see Tables 1 and 6).
1 AIN11/REF
Analog Input 11/Reference Input or Output. Selected in
the setup register (see Tables 1 and 6).
5 C4 13 13 SCL Clock Input
6 C3 14 14 SDA Data Input/Output
7 B1–B4, C2 15 15 GND Ground
8C1 16 16 V
DD
Positive Supply. Bypass to GND with a 0.1_F capacitor.
2, 3, 4 N.C. No Connection. Not internally connected.
t
HD:STA
t
SU:DAT
t
HIGH
t
R
t
F
t
HD:DAT
t
HD:STA
S
Sr
A
SCL
SDA
t
SU:STA
t
LOW
t
BUF
t
SU:STO
PS
t
HD:STA
t
SU:DAT
t
HIGH
t
FCL
t
HD:DAT
t
HD:STA
S Sr A
SCL
SDA
t
SU:STA
t
LOW
t
BUF
t
SU:STO
S
t
RCL
t
RCL1
HS MODE F/S MODE
A. F/S-MODE 2-WIRE SERIAL-INTERFACE TIMING
B. HS-MODE 2-WIRE SERIAL-INTERFACE TIMING
t
FDA
t
RDA
t
t
R
t
F
P
Figure 1. 2-Wire Serial-Interface Timing
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I
2
C,
10-Bit ADCs in Ultra-Small Packages
9
Maxim Integrated
Detailed Description
The MAX11606–MAX11611 analog-to-digital converters
(ADCs) use successive-approximation conversion tech-
niques and fully differential input track/hold (T/H) cir-
cuitry to capture and convert an analog signal to a
serial 12-bit digital output. The MAX11606/MAX11607
are 4-channel ADCs, the MAX11608/MAX11609 are
8-channel ADCs, and the MAX11610/MAX11611 are
12-channel ADCs. These devices feature a high-speed
2-wire serial interface supporting data rates up to
1.7MHz. Figure 2 shows the simplified internal structure
for the MAX11610/MAX11611.
Power Supply
The MAX11606–MAX11611 operates from a single sup-
ply and consumes 670µA (typ) at sampling rates up to
94.4ksps. The MAX11607/MAX11609/MAX11611 feature
a 2.048V internal reference and the MAX11606/
MAX11608/MAX11610 feature a 4.096V internal refer-
ence. All devices can be configured for use with an
external reference from 1V to V
DD
.
Analog Input and Track/Hold
The MAX11606–MAX11611 analog-input architecture
contains an analog-input multiplexer (mux), a fully dif-
ferential track-and-hold (T/H) capacitor, T/H switches, a
comparator, and a fully differential switched capacitive
digital-to-analog converter (DAC) (Figure 4).
In single-ended mode, the analog-input multiplexer con-
nects C
T/H
between the analog input selected by
CS[3:0] (see the
Configuration/Setup Bytes (Write
Cycle)
section) and GND (Table 3). In differential mode,
the analog- input multiplexer connects C
T/H
to the + and
- analog inputs selected by CS[3:0] (Table 4).
During the acquisition interval, the T/H switches are in
the track position and C
T/H
charges to the analog input
ANALOG
INPUT
MUX
AIN1
AIN11/REF
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN0
SCL
SDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROL
LOGIC
REFERENCE
4.096V (MAX11610)
2.048V (MAX11611)
INTERNAL
OSCILLATOR
OUTPUT SHIFT
REGISTER
AND RAM
REF
T/H
10-BIT
ADC
V
DD
GND
MAX11610
MAX11611
Figure 2. MAX11610/MAX11611 Functional Diagram
V
DD
I
OL
I
OH
V
OUT
400pF
SDA
Figure 3. Load Circuit

MAX11610EEE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 10-Bit 12Ch 94.4sps 5.5V Precision ADC
Lifecycle:
New from this manufacturer.
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