MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I
2
C,
10-Bit ADCs in Ultra-Small Packages
4
Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V
DD
= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V
REF
= 2.048V
(MAX11607/MAX11609/MAX11611), V
REF
= 4.096V (MAX11606/MAX11608/MAX11610), f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless other-
wise noted. Typical values are at T
A
= +25°C. See Tables 1–5 for programming notation.) (Note 1)
TIMING CHARACTERISTICS (Figure 1)
(V
DD
= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V
DD
= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V
REF
= 2.048V
(MAX11607/MAX11609/MAX11611), V
REF
= 4.096V (MAX11606/MAX11608/MAX11610), f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless other-
wise noted. Typical values are at T
A
= +25°C. See Tables 1–5 for programming notation.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS
Power-Supply Rejection Ratio PSRR Full-scale input (Note 10) ±0.01 ±0.5 LSB/V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS FOR FAST MODE
Serial-Clock Frequency f
SCL
400 kHz
Bus Free Time Between a
STOP (P) and a
START (S) Condition
t
BUF
1.3 µs
Hold Time for START (S) Condition t
HD
,
STA
0.6 µs
Low Period of the SCL Clock t
LOW
1.3 µs
High Period of the SCL Clock t
HIGH
0.6 µs
Setup Time for a Repeated START
Condition (Sr)
t
SU
,
STA
0.6 µs
Data Hold Time t
HD
,
DAT
(Note 11) 0 900 ns
Data Setup Time t
SU
,
DAT
100 ns
Rise Time of Both SDA and SCL
Signals, Receiving
t
R
Measured from 0.3V
DD
to 0.7V
DD
20 + 0.1C
B
300 ns
Fall Time of SDA Transmitting
t
F
Measured from 0.3V
DD
to 0.7V
DD
(Note 12) 20 + 0.1C
B
300 ns
Setup Time for STOP (P) Condition t
SU
,
STO
0.6 µs
Capacitive Load for Each Bus Line C
B
400 pF
Pulse Width of Spike Suppressed t
SP
50 ns
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C
B
= 400pF, Note 13)
Serial-Clock Frequency f
SCLH
(Note 14) 1.7 MHz
Hold Time, Repeated START
Condition (Sr)
t
HD
,
STA
160 ns
Low Period of the SCL Clock t
LOW
320 ns
High Period of the SCL Clock t
HIGH
120 ns
Setup Time for a Repeated START
Condition (Sr)
t
SU
,
STA
160 ns
Data Hold Time t
HD
,
DAT
(Note 11) 0 150 ns
Data Setup Time t
SU
,
DAT
10 ns
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I
2
C,
10-Bit ADCs in Ultra-Small Packages
5
Maxim Integrated
Note 1: All WLP devices are 100% production tested at T
A
= +25°C. Specifications over temperature limits are guaranteed by
design and characterization.
Note 2: For DC accuracy, the MAX11606/MAX11608/MAX11610 are tested at V
DD
= 5V and the MAX11607/MAX11609/MAX11611
are tested at V
DD
= 3V. All devices are configured for unipolar, single-ended inputs.
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 4: Offset nulled.
Note 5: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to V
DD
.
Note 8: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11), decouple AIN_/REF to GND with a
0.1µF capacitor and a 2kΩ series resistor (see the
Typical Operating Circuit
).
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µV
P-P
.
Note 10: Measured as follows for the MAX11607/MAX11609/MAX11611:
and for the MAX11606/MAX11608/MAX11610, where N is the number of bits:
Note 11: A master device must provide a data hold time for SDA (referred to V
IL
of SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 12: The minimum value is specified at T
A
= +25°C.
Note 13: C
B
= total capacitance of one bus line in pF.
Note 14: f
SCL
must meet the minimum clock low time plus the rise/fall times.
VVVV
V
VV
FS FS
REF
N
(. ) (. )
(. . )
55 45
21
55 45
[]
×
VVVV
V
VV
FS FS
REF
N
(. ) (. )
(. . )
36 27
21
36 27
[]
×
TIMING CHARACTERISTICS (Figure 1) (continued)
(V
DD
= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V
DD
= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V
REF
= 2.048V
(MAX11607/MAX11609/MAX11611), V
REF
= 4.096V (MAX11606/MAX11608/MAX11610), f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless other-
wise noted. Typical values are at T
A
= +25°C. See Tables 1–5 for programming notation.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Rise Time of SCL Signal
(Current Source Enabled)
t
RCL
Measured from 0.3V
DD
to 0.7V
DD
20 80 ns
Rise Time of SCL Signal after
Acknowledge Bit
t
RCL1
Measured from 0.3V
DD
to 0.7V
DD
20 160 ns
Fall Time of SCL Signal t
FCL
Measured from 0.3V
DD
to 0.7V
DD
20 80 ns
Rise Time of SDA Signal t
RDA
Measured from 0.3V
DD
to 0.7V
DD
20 160 ns
Fall Time of SDA Signal t
FDA
Measured from 0.3V
DD
to 0.7V
DD
(Note 12) 20 160 ns
Setup Time for STOP (P) Condition t
SU
,
STO
160 ns
Capacitive Load for Each Bus Line C
B
400 pF
Pulse Width of Spike Suppressed t
SP
(Notes 11 and 14) 0 10 ns
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I
2
C,
10-Bit ADCs in Ultra-Small Packages
6
Maxim Integrated
Typical Operating Characteristics
(V
DD
= 3.3V (MAX11607/MAX11609/MAX11611), V
DD
= 5V (MAX11606/MAX11608/MAX11610), f
SCL
= 1.7MHz, external clock,
f
SAMPLE
= 94.4ksps, single-ended, unipolar, T
A
= +25°C, unless otherwise noted.)
-0.3
-0.1
-0.2
0.1
0
0.2
0.3
0 1000
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
MAX11606 toc01
DIGITAL OUTPUT CODE
DNL (LSB)
400200 600 800
-0.5
-0.2
-0.3
-0.4
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 400200 600 800 1000
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
MAX11606 toc02
DIGITAL OUTPUT CODE
INL (LSB)
-160
-140
-120
-100
-80
-60
-40
-20
0
0 10k 20k 30k 40k 50k
FFT PLOT
MAX11606 toc03
FREQUENCY (Hz)
AMPLITUDE (dBc)
f
SAMPLE
= 94.4ksps
f
IN
= 10kHz
300
400
350
500
450
600
550
650
750
700
800
-40 -10 5-25 20 35 50 65 80
SUPPLY CURRENT
vs. TEMPERATURE
MAX11606 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
INTERNAL REFERENCE
MAX11610/MAX11608/
MAX11606
MAX11610/MAX11608/
MAX11606
MAX11611/MAX11609/
MAX11607
MAX11611/MAX11609/
MAX11607
INTERNAL REFERENCE
EXTERNAL REFERENCE
EXTERNAL REFERENCE
SETUP BYTE
EXT REF: 10111011
INT REF: 11011011
0
0.2
0.1
0.4
0.3
0.5
0.6
2.7 5.2
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX11606 toc05
SUPPLY VOLTAGE (V)
I
DD
(μA)
3.73.2 4.2 4.7
SDA = SCL = V
DD
0
0.10
0.05
0.20
0.15
0.30
0.25
0.35
0.45
0.40
0.50
-40 -10 5
-25
20 35 50 65 80
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX11606 toc06
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
MAX11611/MAX11609/MAX11607
MAX11610/MAX11608/MAX11606
200
300
400
600
500
700
800
020406080100
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE (EXTERNAL CLOCK)
MAX11606 toc08
CONVERSATION RATE (ksps)
AVERAGE I
DD
(μA)
A
B
MAX11611/MAX11609/MAX11607
A) INTERNAL REFERENCE ALWAYS ON
B) EXTERNAL REFERENCE

MAX11610EEE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 10-Bit 12Ch 94.4sps 5.5V Precision ADC
Lifecycle:
New from this manufacturer.
Delivery:
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