LTC4070
7
4070fc
operaTion
The LTC4070 provides a simple, reliable, and high
performance battery protection and charging solution
by preventing the battery voltage from exceeding a
programmed level. Its shunt architecture requires just
one resistor between the input supply and the battery to
handle a wide range of battery applications. When the
input supply is removed and the battery voltage is below
the high battery output threshold, the LTC4070 consumes
just 450nA from the battery.
While the battery voltage is below the programmed float
voltage, the charge rate is determined by the input voltage,
the battery voltage, and the input resistor:
I
CHG
=
V
IN
− V
BAT
R
As the battery voltage approaches the float voltage, the
LTC4070 shunts current away from the battery thereby
reducing the charge current. The LTC4070 can shunt up to
50mA with float voltage accuracy of ±1% over temperature.
The shunt current limits the maximum charge current, but
the 50mA internal capability can be increased by adding
an external P-channel MOSFET.
Adjustable Float Voltage, V
FLOAT
A built-in 3-state decoder connected to the ADJ pin provides
three programmable float voltages: 4.0V, 4.1V, or 4.2V.
The float voltage is programmed to 4.0V when ADJ is tied
to GND, 4.1V when ADJ is floating, and 4.2V when ADJ
is tied to V
CC
. The state of the ADJ pin is sampled about
once every 1.5 seconds. When it is being sampled, the
LTC4070 applies a relatively low impedance voltage at the
ADJ pin. This technique prevents low level board leakage
from corrupting the programmed float voltage.
NTC Qualified Float Voltage, DV
FLOAT(NTC)
The NTC pin voltage is compared against an internal
resistor divider tied to the NTCBIAS pin. This divider
has tap points that are matched to the NTC thermistor
resistance/temperature conversion table for a Vishay
thermistor with a B
25/85
value of 3490 at temperatures of
40°C, 50°C, 60°C, and 70°C.
Battery temperature conditioning adjusts the float volt-
age down to V
FLOAT_EFF
when the NTC thermistor indi-
cates that the battery temperature is too high. For a 10k
thermistor with a B
25/85
value of 3490 such as the Vishay
NTHS0402N02N1002F, and a 10k NTCBIAS resistor, each
10°C increase in temperature above 40°C causes the float
voltage to drop by a fixed amount, DV
FLOAT(NTC)
, depend-
ing on ADJ. If ADJ is at GND, the float voltage steps down
by 50mV for each 10°C temperature increment. If ADJ
is floating, the step size is 75mV. And if ADJ is at V
CC
,
the step size is 100mV. Refer to Table 1 for the range of
V
FLOAT_EFF
programming.
Table 1. NTC Qualified Float Voltage
ADJ DV
FLOAT(NTC
) TEMPERATURE V
NTC
AS % OF NTCBIAS
V
FLOAT_
EFF
GND 50mV T < 40°C
40°C ≤ T < 50°C
50°C ≤ T < 60°C
60°C ≤ T < 70°C
70°C < T
V
NTC
> 36.5%
29.0% < V
NTC
≤ 36.5%
22.8% < V
NTC
≤ 29.0%
17.8% < V
NTC
≤ 22.8%
V
NTC
≤ 17.8%
4.000V
3.950V
3.900V
3.850V
3.800V
Float 75mV T < 40°C
40°C ≤ T < 50°C
50°C ≤ T < 60°C
60°C ≤ T < 70°C
70°C ≤ T
V
NTC
> 36.5%
29.0% < V
NTC
≤ 36.5%
22.8% < V
NTC
≤ 29.0%
17.8% < V
NTC
≤ 22.8%
V
NTC
≤ 17.8%
4.100V
4.025V
3.950V
3.875V
3.800V
V
CC
100mV T < 40°C
40°C ≤ T < 50°C
50°C ≤ T < 60°C
60°C ≤ T < 70°C
70°C ≤ T
V
NTC
> 36.5%
29.0% < V
NTC
≤ 36.5%
22.8%< V
NTC
≤ 29.0%
17.8% < V
NTC
≤ 22.8%
V
NTC
≤ 17.8%
4.200V
4.100V
4.000V
3.900V
3.800V
For all ADJ pin settings the lowest float voltage setting is
3.8V = V
FLOAT
– 4 • DV
FLOAT(NTC)
= V
FLOAT_MIN
. This occurs
at NTC thermistor temperatures above 70°C, or if the NTC
pin is grounded.
To conserve power in the NTCBIAS and NTC resistors, the
NTCBIAS pin is sampled at a low duty cycle at the same
time that the ADJ pin state is sampled.
High Battery Status Output: HBO
The HBO pin pulls high when V
CC
rises to within V
HBTH
of
the programmed float voltage, V
FLOAT_EFF
, including NTC
qualified float voltage adjustments.
If V
CC
drops below the float voltage by more than V
HBTH
+
V
HBHY
the HBO pin pulls low to indicate that the battery is
not at full charge. The input supply current of the LTC4070
drops to less than 450nA (typ) as the LTC4070 no longer
shunts current to protect the battery. The NTCBIAS sample
clock slows to conserve power, and the DRV pin is pulled
up to V
CC
.
