XC18V00 Series In-System-Programmable Configuration PROMs
DS026 (v5.2) January 11, 2008 www.xilinx.com
Product Specification 24
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm
. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
06/11/03 4.0 Major revision.
• Added alternate IDCODES to Ta bl e 5.
• Discontinued XC18V256 density.
• Eliminated industrial ordering combinations.
• Extended commercial temperature range.
• Added MultiPRO Desktop Tool support.
• Changed T
HOE
and T
HCE
to 250 ns in the tables on <RD Red>page 17 and <RD Red>page 18.
• Made change in capacitance values "DC Characteristics Over Operating Conditions".
• Added Note (3) to Tabl e 1.
• Other minor edits.
12/15/03 4.1 Added specification (4.7 kΩ) for recommended pull-up resistor on OE/RESET
pin to section Reset
and Power-On Reset Activation, page 14.
Added paragraph to section Standby Mode, page 14, concerning use of a pull-up resistor and/or
buffer on the DONE pin.
04/05/04 5.0 Major revision.
• Figure 2: Revised configuration bitstream lengths for most Virtex-II FPGAs.
• Replaced previous schematics in Figures 5, 6, 7(a), 7(b), and 7(c) with new Figure 5, Figure 6,
Figure 7, and Figure 8.
• Replaced previous Figure 8 with new Figure 9.
• Replaced previous power-on text section with new Reset and Power-On Reset Activation,
page 14.
• Added specification table Supply Voltage Requirements for Power-On Reset and Power-Down,
page 15.
• Added Footnote (5) to:
♦ Specification table AC Characteristics Over Operating Conditions When Cascading for
XC18V04 and XC18V02, page 19.
♦ Specification table AC Characteristics Over Operating Conditions When Cascading for
XC18V01 and XC18V512, page 20.
• Numerous copyedits and wording changes/clarifications throughout.
07/20/04 5.0.1 Tabl e 2: Removed reference to XC2VP125 FPGA.
03/06/06 5.1 • Added Pb-free packages to Features, page 1, Pinout Diagrams, page 4,"Ordering Information",
Valid Ordering Combinations, page 21and Marking Information, page 22.
• Removed maximum soldering temperature (T
SOL
) from Absolute Maximum Ratings
(1,2)
,
page 15. Refer to Xilinx Device Package User Guide for package soldering guidelines.
• Added information to Tabl e 5 regarding variable JTAG IDCODE revision field.
01/11/08 5.2 • Updated document template.
• Updated URLs.
• Tied RDWR_B and CS_B to GND to ensure valid logic-level Low in FPGA SelectMAP mode in
Figure 6, page 11 and Figure 8, page 13.
• Updated "Marking Information," page 22 for 20-pin packaging.
