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ADN2526ACPZ-R7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
ADN2526 Data Sheet
Rev. B | Page 12 of 16
VCC
MSET
800Ω
200Ω
VCC
07511-026
Figure 26. Equivalent Circuit of the MSET Pin
VCC VCC
3.3Ω
3.3Ω
25Ω
IMODP
IMODN
25Ω
07511-027
Figure 27. Equivalent IMODP and IMODN Pins, As Seen From Laser Side
The recommended configuration of the MSET, IMODP,
and IMODN pins is shown in Figure 28. See Tabl e 7 for the
recommended components.
ADN2526
MSET
V
MSET
VEE
IMODP
IBIAS
VCC
L
C
TOSA
L
IMODN
Z
0
= 25Ω Z
0
= 25Ω
VCC
VCC
L
C
L
Z
0
= 25Ω Z
0
= 25Ω
07511-028
Figure 28. Recommended Configuration for the MSET, IMODP, and IMODN Pins
The ratio between the voltage applied to the MSET pin and the
differential modulation current available at the IMODP and
IMODN pins is a function of the load resistance value, as shown
in Figure 29.
DIFFERENTIAL LOAD RESISTANCE (
Ω)
I
MOD
/V
MSET
(mA/V)
07511-029
MINIMUM
MAXIMUM
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
220
210
0 10
20 30 40 50 60
TYPICAL
Figure 29. MSET Voltage-to-Modulation Current Ratio vs.
Differential Load Resistance
Using the resistance of the TOSA, the user can calculate the
voltage range that should be applied to the MSET pin to generate
the required modulation current range (see the example in the
Applications Information section).
The circuit used to drive the MSET voltage must be able to
drive the 1 kΩ resistance of the MSET pin. To be able to drive
80 mA modulation currents through the differential load, the
output stage of the ADN2526 (the IMODP and IMODN pins)
must be ac-coupled to the load. The voltages at these pins have
a dc component equal to VCC and an ac component with
single-ended, peak-to-peak amplitude of IMOD × 25 Ω. This is
the case even if the load impedance is less than 50 Ω differential,
because the transmission line characteristic impedance sets the
peak-to-peak amplitude. For proper operation of the output stage,
the voltages at the IMODP and IMODN pins must be between
the compliance voltage specifications for these pins over supply,
temperature, and modulation current range, as shown in Figure 30.
See the Applications Information section for examples of
headroom calculations.
IMODP, IMODN
VCC
VCC – 1.1V
VCC + 1.1V
NORMAL OPERATION REGION
07511-030
Figure 30. Allowable Range for the Voltage at IMODP and IMODN
LOAD MISTERMINATION
Due to its excellent S22 performance, the ADN2526 can drive
differential loads that range from 5 Ω to 50 Ω. In practice, many
TOSAs have differential resistance less than 50 Ω. In this case, with
50 Ω differential transmission lines connecting the ADN2526 to
the load, the load end of the transmission lines are misterminated.
This mistermination leads to signal reflections back to the driver.
The excellent back-termination in the ADN2526 absorbs these
reflections, preventing their reflection back to the load. This
enables excellent optical eye quality to be achieved, even when
the load end of the transmission lines is significantly mistermi-
nated. The connection between the load and the ADN2526 must
be made with 50 Ω differential (25 Ω single-ended) transmission
lines so that the driver end of the transmission lines is properly
terminated.
Data Sheet ADN2526
Rev. B | Page 13 of 16
CROSSPOINT ADJUSTMENT
The optical eye cross point is adjustable between 35% and 65%
using the cross point adjust (CPA) control input. The equivalent
circuit for the CPA pin is shown in Figure 31. In a default CPA
setting, leave CPA unconnected (maintain pin-to-pin compatibil-
ity with the ADN2525). The internal bias circuit presents about
1.9 V at the CPA pin and the eye cross point is set to 50%. To set
the cross point at various points, apply an external voltage to the
CPA pin.
7kΩ
7kΩ 7kΩ
VCC
CPA
07511-031
Figure 31. Equivalent Circuit for CPA Pin
POWER SEQUENCE
To e nsure reliable operation, the recommended power-up
sequence is: the supply rail to ADN2526 first, then the BSET
pin, followed by the MSET pin, and, finally, the CPA pin.
To turn off the ADN2526, the operation is reversed: shut down
CPA first, then MSET, followed by BSET, and, last, the supply rail.
POWER CONSUMPTION
The power dissipated by the ADN2526 is given by
IBIASVI
V
VCCP
IBIASSUPPLY
MSET
×+
+
×=
13.5
where:
VCC is the power supply voltage.
V
MSET
is the voltage applied to the MSET pin.
I
SUPPLY
is the sum of the currents that flow into VCC, IMODP,
and IMODN, which are sank by the ADN2526 when V
BSET
=
V
MSET
= 0 V, expressed in amps (see Table 1).
V
IBIAS
is the average voltage presented on the IBIAS pin.
IBIAS is the bias current sank by the ADN2526.
Considering V
BSET
/IBIAS = 10 mV/mA as the conversion factor
from V
BSET
to IBIAS, the dissipated power becomes
IBIAS
BSET
SUPPLY
MSET
V
V
I
V
VCCP ×+
+
×=
105.13
To ensure long-term reliable operation, the junction tempera-
ture of the ADN2526 must not exceed 125°C, as specified in
Table 2. For improved heat dissipation, the SFP+ module case
can work as a heat sink, as shown in Figure 32. A compact
optical module is a complex thermal environment, and
calculations of device junction temperature using the package
junction-to-ambient thermal resistance (θ
JA
) do not yield
accurate results.
T
TOP
T
J
T
PAD
DIE
PACKAGE
THERMAL COMPOUND
MODULE CASE
PCB
VIAS
COPPER PLANE
THERMOCOUPLE
07511-032
Figure 32. Typical Optical Module Structure
The parameters in Table 6 can be used to estimate the IC
junction temperature.
Table 6. Definitions
Parameter Description Unit
T
TOP
Temperature at the top of the package °C
T
PAD
Temperature at the package exposed paddle °C
T
J
IC junction temperature °C
P Power dissipation W
θ
J-TOP
Thermal resistance from the IC junction to
the package top
°C/W
θ
J-PAD
Thermal resistance from the IC junction to
the package exposed paddle
°C/W
T
TOP
and T
PAD
can be determined by measuring the temperature
at points inside the module, as shown in Figure 32. The thermo-
couples should be positioned to obtain an accurate measurement
of the package top and paddle temperatures. Using the model
shown in Figure 33, the junction temperature can be calculated by
T
J
=
( )
TOPJ
PADJ
TOPJ
PADPADJ
TOPTOPJ
PADJ
TTP
−
−
−
−
−
−
+
×+×+××
θθ
θθθθ
where:
θ
J-TOP
and θ
J-PAD
are given in Table 2.
P is the power dissipated by the ADN2526.
P
θ
J-TOP
T
PAD
T
TOP
T
TOP
θ
J-PAD
07511-033
Figure 33. Electrical Model for Thermal Calculations
ADN2526 Data Sheet
Rev. B | Page 14 of 16
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
Figure 34 shows the typical application circuit for the ADN2526.
The dc voltages applied to the BSET and MSET pins control the
bias and modulation currents. The bias current can be monitored
as a voltage drop across the 1 kΩ resistor connected between
the IBMON pin and GND. The ALS pin allows the user to turn
on or turn off the bias and modulation currents, depending on
the logic level applied to the pin. The data signal source must be
connected to the DATAP and DATAN pins of the ADN2526
using 50 Ω transmission lines. The modulation current outputs,
IMODP and IMODN, must be connected to the load (TOSA)
using 50 Ω differential (25 Ω single-ended) transmission lines.
It is recommended that the components shown in Table 7 be
used between the ADN2526 and the TOSA for an example ac
coupling circuit. For up-to-date component recommendations,
contact your local Analog Devices, Inc., sales representative.
Working with a TOSA laser sample, the circuit in Figure 34
delivers optical performance shown in Figure 15 and Figure 16.
For additional applications information and optical eye perfor-
mance of other laser samples, contact your local Analog Devices
sales representative.
LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2526 operates,
care should be taken when designing the PCB layout to obtain
optimum performance. Well controlled transmission line
impedance must be used for the high speed signal paths. The
length of the transmission lines must be kept to a minimum to
reduce losses and pattern-dependent jitter. The PCB layout
must be symmetrical, on both the DATAP and DATAN inputs
and the IMODP and IMODN outputs, to ensure a balance
between the differential signals. All VCC and VEE pins must be
connected to solid copper planes by using low inductance
connections. When the connections are made through vias,
multiple vias should be used in parallel to reduce the parasitic
inductance. Each VEE pin must be locally decoupled with high
quality capacitors. If proper decoupling cannot be achieved
using a single capacitor, the user can use multiple capacitors in
parallel for each VEE pin. A 20 µF tantalum capacitor must be
used as a general decoupling capacitor for the entire module. For
guidelines on the surface-mount assembly of the ADN2526, see
the Amkor Technology® Application Notes for Surface Mount
Assembly of Amkor’s MicroLeadFrame® (MLF®) Packages.
Table 7. Recommended Components for AC-Coupling
Component Value Description
R1, R2
36 Ω
0603 size resistor
R3, R4 200 Ω 0603 size resistor
C3, C4 100 nF 0603 size capacitor, Phycomp 223878615649
L2, L3 20 nH 0402 size inductor, Murata LQW15AN20NJ0
L6, L7 0402 size ferrite Murata BLM15HG102SN1
L1, L4, L5, L8 10 µH 0603 size inductor, Murata LQM21FN100M70L
CPA
MSET
CPA ALS VEE
BSET IBMON
IBIAS VEE
VCC
DATAP
DATAN
VCC
VCC
IMODP
IMODN
VCC
DATAP
DATAN
C1
C2
MSET
BSET
R5
1kΩ
ADN2526
Z
0
= 50Ω Z
0
= 25Ω Z
0
= 25Ω
Z
0
= 50Ω
GND
VCC
GND
VCC
TOSA
C4
C7
200µF
L2
L1
R1
3.3V
VCC VCC
VCC
VCC
VCC
TP1
C5
10nF
GND
GND
VCC
C6
10nF
GND
ALS
L7
L8
R4
L6
L5
R3
VCC
L3
L4
R2
VCC
Z
0
= 25Ω Z
0
= 25Ω
C3
GND
07511-034
Figure 34. Typical Application Circuit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ADN2526ACPZ-R7

Mfr. #:
Buy ADN2526ACPZ-R7
Manufacturer:
Analog Devices Inc.
Description:
Laser Drivers 10G 25 Ohm Diff Active Backmatch Laser
Lifecycle:
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