Data Sheet ADN2526
Rev. B | Page 15 of 16
DESIGN EXAMPLE
This design example covers:
• Headroom calculations for the IBIAS, IMODP, and
IMODN pins.
• Calculation of the typical voltage required at the BSET and
MSET pins to produce the desired bias and modulation
currents.
This design example assumes that the resistance of the TOSA is
25 Ω, the forward voltage of the laser at low current is V
F
= 1 V,
IBIAS = 40 mA, IMOD = 60 mA, and VCC = 3.3 V.
Headroom Calculations
To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
specifications in Table 1.
Considering the typical application circuit shown in Figure 34,
the voltage at the IBIAS pin can be written as
V
IBIAS
= VCC − V
F
− (IBIAS × R
TOSA
) − V
LA
where:
VCC is the supply voltage.
V
F
is the forward voltage across the laser at low current.
R
TOSA
is the resistance of the TOSA.
V
LA
is the dc voltage drop across L5, L6, L7, and L8.
For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.6 V, as specified by the minimum
IBIAS compliance specification in Table 1.
Assuming that the voltage drop across the 25 Ω transmission
lines is negligible and that V
LA
= 0 V, V
F
= 1 V, a n d IBIAS =
40 mA
V
IBIAS
= 3.3 − 1 − (0.04 × 25) = 1.3 V
V
IBIAS
= 1.3 V > 0.6 V, which satisfies the requirement.
The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by
V
COMPLIANCE_MAX
= VCC − 0.75 − 4.4 × IBIAS (2)
For this example,
V
COMPLIANCE_MAX
= VCC – 0.75 − 4.4 × 0.04 = 2.53 V
V
IBIAS
= 1.3 V < 2.53 V, which satisfies the requirement.
To calculate the headroom at the modulation current pins
(IMODP and IMODN), the voltage has a dc component equal
to VCC, due to the ac-coupled configuration, and a swing equal
to IMOD × 25 Ω. For proper operation of the ADN2526, the
voltage at each modulation output pin should be within the
normal operation region shown in Figure 30.
V
LB
is the dc voltage drop across L1, L2, L3, and L4. Assuming
that V
LB
= 0 V and IMOD = 60 mA, the minimum voltage at the
modulation output pins is equal to
VCC − (IMOD × 25)/2 = VCC − 0.75
VCC − 0.75 > VCC − 1.1 V, which satisfies the requirement.
The maximum voltage at the modulation pins is equal to
VCC + (IMOD × 25)/2 = VCC + 0.75
VCC + 0.75 < VCC + 1.1 V, which satisfies the requirement.
Headroom calculations must be repeated for the minimum and
maximum values of the required IBIAS and IMOD ranges to
ensure proper device operation over all operating conditions.
BSET and MSET Pin Voltage Calculation
To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2526 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required IBIAS range can be calculated using the BSET voltage
to IBIAS gain specified in Table 1. Assuming that IBIAS = 40 mA
and the typical IBIAS/V
BSET
ratio of 100 mA/V, the BSET voltage
is given by
V4.0
100
40
mA/V100
(mA)
===
IBIAS
V
BSET
The BSET voltage range can be calculated using the required
IBIAS range and the minimum and maximum BSET voltage to
IBIAS gain values specified in Table 1.
The voltage required at the MSET pin to produce the desired
modulation current can be calculated using
where K is the MSET voltage to IMOD ratio.
The value of K depends on the actual resistance of the TOSA.
It can be read using the plot shown in Figure 29. For a TOSA
resistance of 25 Ω, the typical value of K is equal to 120 mA/V.
Assuming that IMOD = 60 mA and using the preceding
equation, the MSET voltage is given by
V5.0
120
60
mA/V120
(mA)
===
IMOD
V
MSET
The MSET voltage range can be calculated using the required
IMOD range and the minimum and maximum K values. These
can be obtained from the minimum and maximum curves in
Figure 29.
