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ADCMP582BCPZ-WP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
Ultrafast SiGe
Voltage Comparators
Data Sheet
ADCMP580/ADCMP581/ADCMP582
Rev. B Document Feedback
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FEATURES
180 ps propagation delay
25 ps overdrive and slew rate dispersion
8 GHz equivalent input rise time bandwidth
100 ps minimum pulse width
37 ps typical output rise/fall
10 ps deterministic jitter (DJ)
200 fs random jitter (RJ)
−2 V to +3 V input range with +5 V/−5 V supplies
On-chip terminations at both input pins
Resistor-programmable hysteresis
Differential latch control
Power supply rejection > 70 dB
APPLICATIONS
Automatic test equipment (ATE)
High speed instrumentation
Pulse spectroscopy
Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Clock and data signal restoration
FUNCTIONAL BLOCK DIAGRAM
V
P
NONINVERTING
INPUT
V
TP
TERMINATION
V
CCI
V
CCO
V
EE
V
EE
V
TN
TERMINATION
V
N
INVERTING
INPUT
LE INPUTHYS
Q OUTPUT
Q OUTPUT
LE INPUT
ADCMP580/
ADCMP581/
ADCMP582
CML/ECL/
PECL
04672-001
Figure 1.
GENERAL DESCRIPTION
The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage
comparators fabricated on the Analog Devices, Inc. proprietary
XFCB3 Silicon Germanium (SiGe) bipolar process. The
ADCMP580 features CML output drivers, the ADCMP581
features reduced swing ECL (negative ECL) output drivers, and
the ADCMP582 features reduced swing PECL (positive ECL)
output drivers.
All three comparators offer 180 ps propagation delay and 100 ps
minimum pulse width for 10 Gbps operation with 200 fs random
jitter (RJ). Overdrive and slew rate dispersion are typically less
than 15 ps.
The ±5 V power supplies enable a wide −2 V to +3 V input
range with logic levels referenced to the CML/NECL/PECL
outputs. The inputs have 50 Ω on-chip termination resistors
with the optional capability to be left open (on an individual
pin basis) for applications requiring high impedance input.
The CML output stage is designed to directly drive 400 mV into
50 Ω transmission lines terminated to ground. The NECL output
stages are designed to directly drive 400 mV into 50 Ω terminated
to −2 V. e PECL output stages are designed to directly drive
400 mV into 50 Ω terminated to V
CCO
− 2 V. High speed latch
and programmable hysteresis are also provided. The differential
latch input controls are also 50 Ω terminated to an independent
V
TT
pin to interface to either CML or ECL or to PECL logic.
The ADCMP580/ADCMP581/ADCMP582 are available in a
16-lead LFCSP.
ADCMP580/ADCMP581/ADCMP582 Data Sheet
Rev. B | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Information ......................................................................... 5
Absolute Maximum Ratings ............................................................ 6
Thermal Considerations .............................................................. 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Typical Application Circuits .......................................................... 11
Applications Information .............................................................. 12
Power/Ground Layout and Bypassing ..................................... 12
ADCMP580/ADCMP581/ADCMP582 Family of Output
Stages ............................................................................................ 12
Using/Disabling the Latch Feature ........................................... 12
Optimizing High Speed Performance ..................................... 13
Comparator Propagation Delay Dispersion ............................... 13
Comparator Hysteresis .............................................................. 14
Minimum Input Slew Rate Requirement ................................ 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
4/16—Rev. A to Rev. B
Deleted Figure 4; Renumbered Sequentially................................. 7
Changes to Figure 3 and Table 4 ..................................................... 7
Changes to Figure 4 .......................................................................... 8
Added Table 5; Renumbered Sequentially .................................... 8
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
8/07—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changes to Table 4 ............................................................................ 7
Changes to Figure 9 .......................................................................... 8
Changes to Figure 21, Figure 22, and Figure 23 ......................... 10
Changes to Using/Disabling the Latch Feature .......................... 11
Changes to Comparator Hysteresis Section and Figure 29 ....... 13
Changes to Ordering Guide .......................................................... 14
7/05—Revision 0: Initial Version
Data Sheet ADCMP580/ADCMP581/ADCMP582
Rev. B | Page 3 of 16
SPECIFICATIONS
V
CCI
= 5.0 V; V
EE
= −5.0 V; V
CCO
= 3.3 V; T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DC INPUT CHARACTERISTICS
Input Voltage Range V
P
, V
N
−2.0 +3.0 V
Input Differential Range −2.0 +2.0 V
Input Offset Voltage V
OS
−10.0 ±4 +10.0 mV
Offset Voltage Temperature Coefficient ΔV
OS
/d
T
10 µV/°C
Input Bias Current I
P
, I
N
Open termination 15 30.0 µA
Input Bias Current Temperature Coefficient
ΔI
B
/d
T
50
nA/°C
Input Offset Current +2 ±5.0 µA
Input Resistance 47 to 53 Ω
Input Resistance, Differential Mode Open termination 50 kΩ
Input Resistance, Common Mode Open termination 500 kΩ
Active Gain A
V
48 dB
Common-Mode Rejection Ratio CMRR V
CM
= −2.0 V to +3.0 V 60 dB
Hysteresis R
HYS
= ∞ 1 mV
LATCH ENABLE CHARACTERISTICS
Latch Enable Input Impedance Z
IN
Each pin, V
TT
at ac ground 47 to 53 Ω
Latch-to-Output Delay t
PLOH
, t
PLOL
V
OD
= 200 mV 175 ps
Latch Minimum Pulse Width t
PL
V
OD
= 200 mV 100 ps
ADCMP580 (CML)
Latch Enable Input Range −0.8 0 V
Latch Enable Input Differential
0.2
0.4
0.5
V
Latch Setup Time t
S
V
OD
= 200 mV 95 ps
Latch Hold Time t
H
V
OD
= 200 mV −90 ps
ADCMP581 (NECL)
Latch Enable Input Range −1.8 +0.8 V
Latch Enable Input Differential 0.2 0.4 0.5 V
Latch Setup Time t
S
V
OD
= 200 mV 70 ps
Latch Hold Time t
H
V
OD
= 200 mV −65 ps
ADCMP582 (PECL)
Latch Enable Input Range V
CCO
− 1.8 V
CCO
− 0.8 V
Latch Enable Input Differential 0.2 0.4 0.5 V
Latch Setup Time
t
S
V
OD
= 200 mV
30
ps
Latch Hold Time t
H
V
OD
= 200 mV −25 ps
DC OUTPUT CHARACTERISTICS
ADCMP580 (CML)
Output Impedance Z
OUT
50 Ω
Output Voltage High Level V
OH
50 Ω to GND −0.10 0 +0.03 V
Output Voltage Low Level V
OL
50 Ω to GND −0.50 −0.40 −0.35 V
Output Voltage Differential 50 Ω to GND 340 395 450 mV
ADCMP581 (NECL)
Output Voltage High Level V
OH
50 Ω to −2 V, T
A
= 125°C −0.99 −0.87 −0.75 V
Output Voltage High Level V
OH
50 Ω to −2 V, T
A
= 25°C −1.06 −0.94 −0.82 V
Output Voltage High Level V
OH
50 Ω to −2 V, T
A
= −55°C −1.11 −0.99 −0.87 V
Output Voltage Low Level V
OL
50 Ω to −2 V, T
A
= 125°C −1.43 −1.26 −1.13 V
Output Voltage Low Level V
OL
50 Ω to −2 V, T
A
= 25°C −1.50 −1.33 −1.20 V
Output Voltage Low Level
V
OL
50 Ω to −2 V, T
A
= −55°C
−1.55
−1.38
−1.25
V
Output Voltage Differential 50 Ω to −2.0 V 340 395 450 mV
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ADCMP582BCPZ-WP

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Analog Comparators Ultrafast SiGe VTG
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