ADCMP580/ADCMP581/ADCMP582 Data Sheet
Rev. B | Page 12 of 16
APPLICATIONS INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP580/ADCMP581/ADCMP582 family of comparators
is designed for very high speed applications. Consequently, high
speed design techniques must be used to achieve the specified
performance. It is critically important to use low impedance
supply planes, particularly for the negative supply (V
EE
), the
output supply plane (V
CCO
), and the ground plane (GND).
Individual supply planes are recommended as part of a multilayer
board. Providing the lowest inductance return path for the
switching currents ensures the best possible performance in the
target application.
It is also important to adequately bypass the input and output
supplies. A 1 µF electrolytic bypass capacitor must be placed
within several inches of each power supply pin to ground. In
addition, multiple high quality 0.1 µF bypass capacitors must be
placed as close as possible to each of the V
EE
, V
CCI
, and
V
CCO
supply pins and must be connected to the GND plane with
redundant vias. High frequency bypass capacitors must be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance must be strictly avoided to maximize the
effectiveness of the bypass at high frequencies.
ADCMP580/ADCMP581/ADCMP582 FAMILY OF
OUTPUT STAGES
Specified propagation delay dispersion performance is achieved
by using proper transmission line terminations. The outputs of
the ADCMP580 family comparators are designed to directly
drive 400 mV into 50 Ω cable or microstrip/stripline transmis-
sion lines terminated with 50 Ω referenced to the proper return.
The CML output stage for the ADCMP580 is shown in the
simplified schematic diagram in Figure 23. Each output is back-
terminated with 50 Ω for best transmission line matching. The
outputs of the ADCMP581/ADCMP582 are illustrated in
Figure 24; they must be terminated to −2 V for ECL outputs of
ADCMP581 and V
CCO
− 2 V for PECL outputs of ADCMP582. As
an alternative, Thevenin equivalent termination networks can
also be used. If these high speed signals must be routed more
than a centimeter, either microstrip or stripline techniques are
required to ensure proper transition times and to prevent
excessive output ringing and pulse width-dependent propagation
delay dispersion.
Q
16mA
50
Ω
50Ω
Q
GND
V
EE
04672-024
Figure 23. Simplified Schematic Diagram of the ADCMP580 CML Output Stage
GND/V
CCO
V
EE
Q
Q
04672-025
Figure 24. Simplified Schematic Diagram of the
ADCMP581/ADCMP582 ECL/PECL Output Stage
USING/DISABLING THE LATCH FEATURE
The latch inputs (LE/
LE
) are active low for latch mode and are
internally terminated with 50 Ω resistors to the V
TT
pin. When
using the ADCMP580, V
TT
must be connected to ground. When
using the ADCMP581, V
TT
must be connected to −2 V. When
using the ADCMP582, V
TT
must be connected externally to V
CCO
− 2 V, preferably with its own low inductance plane.
When using the ADCMP580, the latch function can be disabled
by connecting the
LE
pin to V
EE
with an external pull-down
resistor and by leaving the LE pin to ground. To prevent excessive
power dissipation, the resistor must be 1 kΩ for the ADCMP580.
When using the ADCMP581 comparators, the latch can be
disabled by connecting the
LE
pin to V
EE
with an external 750 Ω
resistor and leaving the LE pin connected to −2 V. The idea is to
create an approximate 0.5 V offset using the internal resistor as
half of the voltage divider. Connect the V
TT
pin as recommended.
