Data Sheet ADCMP580/ADCMP581/ADCMP582
Rev. B | Page 13 of 16
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed comparator, proper design and layout
techniques are essential to obtaining the specified performance.
Stray capacitance, inductance, inductive power, and ground
impedances or other layout issues can severely limit performance
and can cause oscillation. Discontinuities along input and output
transmission lines can also severely limit the specified pulse
width dispersion performance.
For applications in a 50 Ω environment, input and output
matching have a significant impact on data-dependent (or
deterministic) jitter (DJ) and pulse width dispersion
performance. The ADCMP580/ADCMP581/ADCMP582
family of comparators provides internal 50 Ω termination
resistors for both V
P
and V
N
inputs. The return side for each
termination is pinned out separately with the V
TP
and V
TN
pins,
respectively. If a 50 Ω termination is desired at one or both of
the V
P
/V
N
inputs, the V
TP
and V
TN
pins can be connected (or
disconnected) to (from) the desired termination potential as
appropriate. The termination potential must be carefully
bypassed using ceramic capacitors as discussed previously to
prevent undesired aberrations on the input signal due to parasitic
inductance in the termination return path. If a 50 Ω termination
is not desired, either one or both of the V
TP
/V
TN
termination pins
can be left disconnected. In this case, the open pins must be left
floating with no external pull downs or bypassing capacitors.
For applications that require high speed operation but do not
have on-chip 50 Ω termination resistors, some reflections
must be expected, because the comparator inputs can no longer
provide matched impedance to the input trace leading up to the
device. It then becomes important to back-match the drive
source impedance to the input transmission path leading to the
input to minimize multiple reflections. For applications in
which the comparator is less than 1 cm from the driving signal
source, the source impedance must be minimized. High source
impedance in combination with parasitic input capacitance of
the comparator could cause undesirable degradation in
bandwidth at the input, thus degrading the overall response. It
is therefore recommended that the drive source impedance be no
more than 50 Ω for best high speed performance.
COMPARATOR PROPAGATION DELAY DISPERSION
The ADCMP580/ADCMP581/ADCMP582 family of comparators
has been specifically designed to reduce propagation delay dis-
persion over a wide input overdrive range of 5 mV to 500 mV.
Propagation delay dispersion is a change in propagation delays that
results from a change in the degree of overdrive or slew rate (how
far or how fast the input signal exceeds the switching threshold).
The overall result is a higher degree of timing accuracy.
Propagation delay dispersion is a specification that becomes
important in critical timing applications, such as data commu-
nications, automatic test and measurement, instrumentation,
and event-driven applications, such as pulse spectroscopy,
nuclear instrumentation, and medical imaging. Dispersion is
defined as the variation in the overall propagation delay as the
input overdrive conditions are changed (see Figure 25 and
Figure 26). For the ADCMP580/ADCMP581/ADCMP582
family of comparators, dispersion is typically <25 ps, because
the overdrive varies from 5 mV to 500 mV, and the input slew
rate varies from 1 V/ns to 10 V/ns. This specification applies for
both positive and negative signals because the
ADCMP580/ADCMP581/ADCMP582 family of comparators
has almost equal delays for positive- and negative-going inputs.
Q/Q OUTPUT
INPUT VOLTAGE
500mV OVERDRIV
5mV OVERDRIVE
DISPERSION
V
N
± V
OS
04672-026
Figure 25. Propagation Delay—Overdrive Dispersion
Q/Q OUTPUT
INPUT VOLTAGE
10V/ns
1V/ns
DISPERSION
V
N
± V
OS
4672-027
Figure 26. Propagation Delay—Slew Rate Dispersion
