Data Sheet ADCMP580/ADCMP581/ADCMP582
Rev. B | Page 7 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Q
LE
V
TP
V
P
V
N
V
TN
Q
GND
GND
V
CCI
LE
V
TT
GND
V
CCI
HYS
V
EE
04672-003
12
11
10
1
3
4
9
2
6
5
7
8
16
15
14
13
ADCMP580/
ADCMP581
TOP VIEW
NOTES
1. THE METALLIC BACK SURFACE OF THE PACKAGE IS NOT ELECTRICALLY
CONNECTED TO ANY PART OF THE CIRCUIT. IT CAN BE LEFT FLOATING FOR
OPTIMAL ELECTRICAL ISOLATION BETWEEN THE PACKAGE HANDLE AND
THE SUBSTRATE OF THE DIE. IT CAN ALSO BE SOLDERED TO THE
APPLICATION BOARD IF IMPROVED THERMAL AND/OR MECHANICAL
STABILITY IS DESIRED.
Figure 3. ADCMP580/ADCMP581 Pin Configuration
Table 4. ADCMP580/ADCMP581 Pin Function Descriptions
Pin No. Mnemonic Description
1 V
TP
Termination Resistor Return Pin for V
P
Input.
2 V
P
Noninverting Analog Input.
3 V
N
Inverting Analog Input.
4 V
TN
Termination Resistor Return Pin for V
N
Input.
5, 16 V
CCI
Positive Supply Voltage.
6
LE
Latch Enable Input Pin, Inverting Side. In compare mode (
LE
= low), the output tracks changes at the input of the
comparator. In latch mode (
LE
= high), the output reflects the input state just prior to the comparator being
placed into latch mode.
LE
must be driven in complement with LE.
7 LE Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the input
of the comparator. In latch mode (LE = low), the output reflects the input state just prior to the comparator being
placed into latch mode. LE must be driven in complement with
LE
.
8 V
TT
Termination Return Pin for the LE/
LE
Input Pins. For the ADCMP580 (CML output stage), this pin must be
connected to ground. For the ADCMP581 (ECL output stage), connect this pin to the –2 V termination potential.
9, 12 GND Digital Ground Pin/Positive Logic Power Supply Terminal. This pin must be connected to the GND pin.
10
Q
Inverting Output.
Q
is logic low if the analog voltage at the noninverting input, V
P
, is greater than the analog
voltage at the inverting input, V
N
, provided that the comparator is in compare mode. See the LE/
LE
descriptions
(Pin 6 to Pin 7) for more information.
11 Q Noninverting Output. Q is logic high if the analog voltage at the noninverting input, V
P
, is greater than the analog
voltage at the inverting input, V
N
, provided that the comparator is in compare mode. See the LE/
LE
descriptions
(Pin 6 to Pin 7) for more information.
13 V
EE
Negative Power Supply.
14 HYS Hysteresis Control. Leave this pin disconnected for zero hysteresis. Connect this pin to the V
EE
supply with a
suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 8 for proper sizing of the HYS
hysteresis control resistor.
15 GND Analog Ground.
EPAD Exposed Pad. The metallic back surface of the package is not electrically connected to any part of the circuit. It
can be left floating for optimal electrical isolation between the package handle and the substrate of the die. It
can also be soldered to the application board if improved thermal and/or mechanical stability is desired.
