Address 07h
Bit 7 Logic 0 (default) adds the 10 bits offset cur-
rent to OUTIN. A logic 1 adds the 10 bits off-
set current to OUTIP.
Address 08h
Bits 7–0 These eight bits define the binary number for
fine-gain adjustment of the QDAC full-scale
current (see the
Gain Adjustment
section). Bit
7 is the MSB. Default is all zeros.
Address 09h
Bits 3–0 These four bits define the binary number for
the coarse-gain adjustment of the QDAC full-
scale current (see the
Gain Adjustment
sec-
tion). Bit 3 is the MSB. Default is all ones.
Address 0Ah, Bits 7–0; Address 0Bh, Bit 1 and Bit 0
These 10 bits represent a binary number that
defines the magnitude of the offset added to
the QDAC output (see the
Offset Adjustment
section). Default is all zeros.
Address 0Bh
Bit 7 Logic 0 (default) adds the 10 bits offset to
OUTQN. A logic 1 adds the 10 bits offset to
OUTQP.
Offset Adjustment
Offset adjustment is achieved by adding a digital code to
the DAC inputs. The code OFFSET (see equation below),
as stored in the relevant control registers, has a range
from 0 to 1023 and a sign bit. The applied DAC offset is
stored in the register, providing an offset adjustment
range of ±1023 LSB codes. The resolution is 1 LSB.
Gain Adjustment
Gain adustment is peformed by varying the full-scale
current according to the following formula:
where I
REF
is the reference current (see the
Reference
Input/Output
section). COARSE is the register content
of registers 05h and 09h for the I- and Q-channel,
respectively. FINE is the register content of register 04h
and 08h for the I- and Q-channel, respectively. The
range of coarse is from 0 to 15, with 15 being the
default. The range for FINE is from 0 to 255 with 0
being the default. The gain can be adjusted in steps of
approximately 0.01dB.
Single-Port/Dual-Port Data-Input Modes
The MAX5894 is capable of capturing data in single-
port and dual-port modes (selected through bit 6,
address 02h). In single-port mode, the data for both
DAC channels is latched on the A port (A13–A0).
The channel for the input data is determined by the
state of the SELIQ/B13 (pin 26) bit. When SELIQ is set
to logic-high, the input data is presented to the
I-channel, when set to logic-low, the input data is
presented to the Q-channel. The unused B-port inputs
(DATACLK/B12, B11–B0) should be grounded when
running in single-port mode.
Dual-port mode, as the name implies, requires that
each channel receives its data from a separate data
bus. SELIQ/B13 and DATACLK/B12 revert to data bit
inputs for the Q-channel in dual-port mode.
The MAX5894 control registers can be programmed to
allow either signed or unsigned binary format (bit 7,
address 02h) data in either single-port or dual-port
mode. Table 3 shows the corresponding DAC output
levels when using signed or unsigned data modes.
Data Synchronization Modes
Data synchronization circuitry is provided to allow oper-
ation with an input data clock. The data clock must be
frequency locked to the DAC clock (f
DAC
), but can
have arbitrary phase with respect to the DAC clock.
The synchronization circuitry allows for phase jitter on
the input data clock of up to ±1 data clock cycles.
Synchronization is initially established when the reset
pin is asynchronously deasserted and the input data
clock has been running for at least four clock cycles.
Subsequently, the MAX5894 monitors the phase rela-
