Power-Down Mode
The MAX5894 features three power-saving modes.
Each DAC can be individually powered down through
bits 2 and 3 of address 00h. The interpolation filters can
also be powered down through bit 4 of address 00h,
preserving the output level of each DAC (the DACs
remain powered). Powering down both DACs automati-
cally puts the MAX5894 into full power-down, including
the interpolation filters.
Applications Information
Frequency Planning
System designers need to take the DAC into account
during frequency planning for high-performance appli-
cations. Proper frequency planning can ensure that
optimal system performance is achieved. The
MAX5894 is designed to deliver excellent dynamic per-
formance across wide bandwidths, as required for
communication systems. As with all DACs, some com-
binations of output frequency and update rate produce
better performance than others.
Harmonics are often folded down into the band of inter-
est. Specifically, if the DAC outputs a frequency close
to f
S
/N, the Mth harmonic of the output signal will be
aliased down to:
Thus, if N ≈ (M + 1), the Mth harmonic will be close to
the output frequency. SFDR performance of a current-
steering DAC is often dominated by 3rd-order harmonic
distortion. If this is a concern, placing the output signal
at a different frequency other than f
S
/4 should be con-
sidered.
Common to interpolating DACs are images near the
divided clocks. In a DAC configured for 4x interpolation,
this applies to images around f
S
/4 and f
S
/2. In a DAC
configured for 8x interpolation, this applies to images
around f
S
/8, f
S
/4, and f
S
/2. Most of these images are
not part of the in-band (0 to f
DATA
/2) SFDR specifica-
tion, though they are a consideration for out-of-band
(f
DATA
/2 - f
DAC
/2) SFDR and may depend on the rela-
tionship of the DATACLK to DAC update clock (see the
Data Clock
section). When specifying the output recon-
struction filter for other than baseband signals, these
images should not be ignored.
Data Clock
The MAX5894 features synchronizers that allow for arbi-
trary phase alignment between DATACLK and
CLKP/CLKN. The DATACLK causes internal switching in
the MAX5894 and the phase between DATACLK (input
mode) to CLKP/CLKN influences the images at
DATACLK. Optimum image rejection is achieved when
DATACLK transitions are aligned with the falling edge of
CLKP. Figure 14 shows the image level near DATACLK
as a function of the DATACLK (input mode) to
CLKP/CLKN phase at 500Msps, 4x interpolation for a
10MHz, -6dBFS output signal.
Clock Interface
The MAX5894 features a flexible differential clock input
(CLKP, CLKN) with a separate supply (AV
CLK
) to
achieve optimum jitter performance. It uses an ultra-low
jitter clock to achieve the required noise density. Clock
jitter must be less than 0.5ps
RMS
to meet the specified
noise density. For that reason, the CLKP/CLKN input
source must be designed carefully. The differential
clock (CLKN and CLKP) input can be driven from a sin-
gle-ended or a differential clock source. Differential
clock drive is required to achieve the best dynamic
performance from the DAC. For single-ended opera-
tion, drive CLKP with a low noise source and bypass
CLKN to GND with a 0.1µF capacitor.
The CLKP and CLKN pins are internally biased to
AV
CLK
/2. This allows the user to AC-couple clock
/4 IMAGES vs. CLKP/CLKN to DATACLK DELAY
