CY7C09389V-7AXC Datasheet CY7C09369V-12AXC, CY7C09289V-12AXC, CY7C09369V-9AXCT | P1-P3

CY7C09269V/79V/89V

CY7C09369V/89V

3.3 V 16K / 32K / 64K × 16 / 18

Synchronous Dual-Port Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 38-06056 Rev. *M Revised March 21, 2016

3.3 V 16K / 32K / 64K × 16 / 18 Synchronous Dual-Port Static RAM

Features

■ True dual-ported memory cells that allow simultaneous access

of the same memory location

■ Six flow through/pipelined devices:

❐ 16K × 16 / 18 organization (CY7C09269V/369V)

❐ 32K × 16 organization (CY7C09279V)

❐ 64K × 16 / 18 organization (CY7C09289V/389V)

■ Three modes:

❐ Flow through

❐ Pipelined

❐ Burst

■ Pipelined output mode on both ports allows fast 100 MHz

operation

■ 0.35 micron CMOS for optimum speed and power

■ High speed clock to data access: 7.5

[1]

, 9, 12 ns (max)

■ 3.3 V low operating power:

❐ Active = 115 mA (typical)

❐ Standby = 10 A (typical)

■ Fully synchronous interface for easier operation

■ Burst counters increment addresses internally:

❐ Shorten cycle times

❐ Minimize bus noise

❐ Supported in flow through and pipelined modes

■ Dual chip enables easy depth expansion

■ Upper and lower byte controls for bus matching

■ Automatic power down

■ Commercial and industrial temperature ranges

■ Pb-free 100-pin TQFP package available

Functional Description

For a complete list of related documentation, click here.

0/1

0b 1a 0a

/Pipe

I/O

8/9L

–I/O

15/17L

I/O

–I/O

7/8L

I/O

Control

Counter/

Address

Decode

–A

13/14/15L

CLK

ADS

CNTEN

CNTRST

True Dual-Ported

RAM Array

0/1

0b1a0a

/Pipe

I/O

Control

Counter/

Address

Decode

14/15/16

8/9

I/O

8/9R

–I/O

15/17R

I/O

–I/O

7/8R

–A

13/14/15R

CLK

ADS

CNTEN

CNTRST

14/15/16

8/9

[2]

[3]

[2]

[3]

[4] [4]

Logic Block Diagram

Notes

1. See Figure 4 on page 8 for Load Conditions.

2. I/O

–I/O

for × 16 devices; I/O

–I/O

for × 18 devices.

3. I/O

–I/O

for × 16 devices. I/O

–I/O

for × 18 devices.

4. A

–A

for 16K; A

–A

for 32K; A

–A

for 64K devices.

CY7C09269V/79V/89V

CY7C09369V/89V

Document Number: 38-06056 Rev. *M Page 2 of 25

Contents

Pin Configurations ...........................................................3

Selection Guide ................................................................5

Pin Definitions ..................................................................5

Functional Overview ........................................................6

Maximum Ratings .............................................................7

Operating Range ...............................................................7

Electrical Characteristics .................................................7

Capacitance ......................................................................7

AC Test Loads and Waveforms .......................................8

Switching Characteristics ................................................9

Switching Waveforms ....................................................10

Read/Write and Enable Operation .................................18

Address Counter Control Operation .............................18

Ordering Information ......................................................19

16K × 16 3.3 V Synchronous Dual-Port SRAM .........19

32K × 16 3.3 V Synchronous Dual-Port SRAM .........19

16K × 18 3.3 V Synchronous Dual-Port SRAM ......... 19

64K × 18 3.3 V Synchronous Dual-Port SRAM ......... 19

Ordering Code Definitions .........................................20

Package Diagrams ..........................................................21

Acronyms ........................................................................22

Document Conventions .................................................22

Units of Measure .......................................................22

Document History Page .................................................23

Sales, Solutions, and Legal Information ......................25

Worldwide Sales and Design Support ....................... 25

Products ....................................................................25

PSoC® Solutions ......................................................25

Cypress Developer Community .................................25

Technical Support .....................................................25

CY7C09269V/79V/89V

CY7C09369V/89V

Document Number: 38-06056 Rev. *M Page 3 of 25

Pin Configurations

Figure 1. 100-pin TQFP pinout (Top View)

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

A9R

A10R

A11R

A12R

A13R

A14R

UBR

LBR

CE1R

CNTRSTR

OER

FT/PIPER

A15R

GND

R/WR

GND

I/O15R

I/O14R

I/O13R

I/O12R

I/O11R

I/O10R

CE0R

CY7C09279V (32K × 16)

CY7C09269V (16K × 16)

A9L

A10L

A11L

A12L

A13L

A14L

UBL

LBL

CE1L

CNTRSTL

OEL

FT/PIPEL

A15L

VCC

R/WL

GND

I/O15L

I/O14L

I/O13L

I/O12L

I/O11L

I/O10L

CE0L

A8L

A7L

A6L

A5L

A4L

A3L

CLKL

A1L

CNTENL

GND

ADSR

A0R

A1R

A0L

A2L

CLKR

CNTENR

A2R

A3R

A4R

A5R

A6R

A7R

A8R

ADSL

34 35 36 424139 403837 43 44 45 5048 494746

I/O9R

I/O8R

I/O7R

VCC

I/O6R

I/O1R

I/O4R

I/O2R

GND

I/O0L

I/O2L

I/O3L

I/O3R

I/O5R

I/O1L

GND

I/O4L

I/O5L

I/O6L

I/O7L

VCC

I/O8L

I/O9L

I/O0R

3332313029282726

CY7C09289V (64K × 16)

[5]

[6]

[7]

[5]

[6]

Notes

5. This pin is NC for CY7C09269V.

6. This pin is NC for CY7C09269V and CY7C09279V.

7. For CY7C09269V and CY7C09279V, pin #18 connected to V

is pin compatible to an IDT 5 V × 16 pipelined device; connecting pin #18 and #58 to GND is pin

compatible to an IDT 5 V × 16 flow through device.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

CY7C09389V-7AXC

Mfr. #:

Buy CY7C09389V-7AXC

Manufacturer:

Cypress Semiconductor

Description:

IC SRAM 1.152M PARALLEL 100TQFP

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

CY7C09389V-7AXC

CY7C09389V-7AXC

Products related to this Datasheet