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CY7C09389V-7AXC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
CY7C09269V/79V/89V
CY7C09369V/89V
Document Number: 38-06056 Rev. *M Page 10 of 25
Switching Waveforms
Figure 5. Read Cycle for Flow Through Output (FT/PIPE = V
IL
)
[21, 22, 23, 24]
Figure 6. Read Cycle for Pipelined Operation (FT/PIPE = V
IH
)
[21, 22, 23, 24]
t
CH1
t
CL1
t
CYC1
t
SC
t
HC
t
DC
t
OHZ
t
OE
t
SC
t
HC
t
SW
t
HW
t
SA
t
HA
t
CD1
t
CKHZ
t
DC
t
OLZ
t
CKLZ
A
n
A
n+1
A
n+2
A
n+3
Q
n
Q
n+1
Q
n+2
CLK
CE
0
CE
1
R/W
ADDRESS
DATA
OUT
OE
t
CH2
t
CL2
t
CYC2
t
SC
t
HC
t
SW
t
HW
t
SA
t
HA
A
n
A
n+1
CLK
CE
0
CE
1
R/W
ADDRESS
DATA
OUT
OE
A
n+2
A
n+3
t
SC
t
HC
t
OHZ
t
OE
t
OLZ
t
DC
t
CD2
t
CKLZ
Q
n
Q
n+1
Q
n+2
1 Latency
Notes
21. OE
is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
22. ADS
= V
IL
, CNTEN and CNTRST = V
IH
.
23. The output is disabled (high impedance state) by CE
0
=V
IH
or CE
1
= V
IL
following the next rising edge of the clock.
24. Addresses do not have to be accessed sequentially since ADS
= V
IL
constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
CY7C09269V/79V/89V
CY7C09369V/89V
Document Number: 38-06056 Rev. *M Page 11 of 25
Figure 7. Bank Select Pipelined Read
[25, 26]
Figure 8. Left Port Write to Flow Through Right Port Read
[27, 28, 29, 30]
Switching Waveforms (continued)
D
3
D
1
D
0
D
2
A
0
A
1
A
2
A
3
A
4
A
5
D
4
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
t
SC
t
HC
t
SA
t
HA
t
SC
t
HC
t
SC
t
HC
t
SC
t
HC
t
CKHZ
t
DC
t
DC
t
CD2
t
CKLZ
t
CD2
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
CH2
t
CL2
t
CYC2
CLK
L
ADDRESS
(B1)
CE
0(B1)
DATA
OUT(B2)
DATA
OUT(B1)
ADDRESS
(B2)
CE
0(B2)
t
SA
t
HA
t
SW
t
HW
t
SD
t
HD
MATCH
VALID
t
CCS
t
SW
t
HW
t
DC
t
CWDD
t
CD1
MATCH
t
SA
t
HA
MATCH
NO
MATCH
NO
VALID VALID
t
DC
t
CD1
CLK
L
R/
W
L
ADDRESS
L
DATA
INL
ADDRESS
R
DATA
OUTR
CLK
R
R/
W
R
Notes
25. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet.
ADDRESS
(B1)
= ADDRESS
(B2)
.
26. UB
, LB, OE and ADS = V
IL
; CE
1(B1)
, CE
1(B2)
, R/W, CNTEN, and CNTRST = V
IH
.
27. The same waveforms apply for a right port write to flow through left port read.
28. CE
0
, UB, LB, and ADS = V
IL
; CE
1
, CNTEN, and CNTRST = V
IH
.
29. OE
= V
IL
for the Right Port, which is being read from. OE = V
IH
for the Left Port, which is being written to.
30. It t
CCS
maximum specified, then data from right port READ is not valid until the maximum specified for t
CWDD
. If t
CCS
>maximum specified, then data is not valid until
t
CCS
+ t
CD1
. t
CWDD
does not apply in this case.
CY7C09269V/79V/89V
CY7C09369V/89V
Document Number: 38-06056 Rev. *M Page 12 of 25
Figure 9. Pipelined Read-to-Write-to-Read (OE = V
IL
)
[31, 32, 33, 34]
Figure 10. Pipelined Read-to-Write-to-Read (OE Controlled)
[31, 32, 33, 34]
Switching Waveforms (continued)
t
CYC2
t
CL2
t
CH2
t
HC
t
SC
t
HW
t
SW
t
HA
t
SA
t
HW
t
SW
t
CD2
t
CKHZ
t
SD
t
HD
t
CKLZ
t
CD2
NO OPERATION WRITEREAD READ
CLK
CE
0
CE
1
R/W
ADDRESS
DATA
IN
DATA
OUT
A
n
A
n+1
A
n+2
A
n+2
D
n+2
A
n+3
A
n+4
Q
n
Q
n+3
t
CYC2
t
CL2
t
CH2
t
HC
t
SC
t
HW
t
SW
t
HA
t
SA
A
n
A
n+1
A
n+2
A
n+3
A
n+4
A
n+5
t
HW
t
SW
t
SD
t
HD
D
n+2
t
CD2
t
OHZ
READ READWRITE
D
n+3
t
CKLZ
t
CD2
Q
n
Q
n+4
CLK
CE
0
CE
1
R/W
ADDRESS
DATA
IN
DATA
OUT
OE
Notes
31. Addresses do not have to be accessed sequentially since ADS
= V
IL
constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
32. Output state (High, LOW, or high impedance) is determined by the previous cycle control signals.
33. CE
0
and ADS = V
IL
; CE
1
, CNTEN, and CNTRST = V
IH
.
34. During “No Operation”, data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

CY7C09389V-7AXC

Mfr. #:
Buy CY7C09389V-7AXC
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 1.152M PARALLEL 100TQFP
Lifecycle:
New from this manufacturer.
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