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CY7C09389V-7AXC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
CY7C09269V/79V/89V
CY7C09369V/89V
Document Number: 38-06056 Rev. *M Page 13 of 25
Figure 11. Flow Through Read-to-Write-to-Read (OE
= V
IL
)
[35, 36, 37, 38]
Switching Waveforms (continued)
t
CH1
t
CL1
t
CYC1
t
SC
t
HC
t
SW
t
HW
t
SA
t
HA
t
SW
t
HW
t
SD
t
HD
A
n
A
n+1
A
n+2
A
n+2
A
n+3
A
n+4
D
n+2
Q
n
Q
n+1
Q
n+3
t
CD1
t
CD1
t
DC
t
CKHZ
t
CD1
t
CD1
t
CKLZ
t
DC
READ
NO
OPERATION
WRITE READ
CLK
CE
0
CE
1
ADDRESS
R/W
DATA
IN
DATA
OUT
Notes
35. ADS
= V
IL
, CNTEN and CNTRST = V
IH
.
36. Addresses do not have to be accessed sequentially since ADS
= V
IL
constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
37. CE
0
and ADS = V
IL
; CE
1
, CNTEN, and CNTRST = V
IH
.
38. During “No Operation”, data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity.
CY7C09269V/79V/89V
CY7C09369V/89V
Document Number: 38-06056 Rev. *M Page 14 of 25
Figure 12. Flow Through Read-to-Write-to-Read (OE Controlled)
[39, 40, 41, 42, 43]
Switching Waveforms (continued)
Q
n
t
CH1
t
CL1
t
CYC1
t
SC
t
HC
t
SW
t
HW
t
SA
t
HA
t
CD1
t
DC
t
OHZ
READ
A
n
A
n+1
A
n+2
A
n+3
A
n+4
A
n+5
D
n+2
D
n+3
t
SW
t
HW
t
SD
t
HD
t
CD1
t
CD1
t
CKLZ
t
DC
Q
n+4
t
OE
WRITE READ
CLK
CE
0
CE
1
ADDRESS
R/W
DATA
IN
DATA
OUT
OE
Notes
39. ADS
= V
IL
, CNTEN and CNTRST = V
IH
.
40. Addresses do not have to be accessed sequentially since ADS
= V
IL
constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
41. CE
0
and ADS = V
IL
; CE
1
, CNTEN, and CNTRST = V
IH
.
42. During “No Operation”, data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity.
43. Output state (High, LOW, or high impedance) is determined by the previous cycle control signals.
CY7C09269V/79V/89V
CY7C09369V/89V
Document Number: 38-06056 Rev. *M Page 15 of 25
Figure 13. Pipelined Read with Address Counter Advance
[44]
Figure 14. Flow Through Read with Address Counter Advance
[44]
Switching Waveforms (continued)
COUNTER HOLD
READ WITH COUNTER
t
SA
t
HA
t
SAD
t
HAD
t
SCN
t
HCN
t
CH2
t
CL2
t
CYC2
t
SAD
t
HAD
t
SCN
t
HCN
Q
x-1
Q
x
Q
n
Q
n+1
Q
n+2
Q
n+3
t
DC
t
CD2
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
CLK
ADDRESS
ADS
DATA
OUT
CNTEN
A
n
t
CH1
t
CL1
t
CYC1
t
SA
t
HA
t
SAD
t
HAD
t
SCN
t
HCN
Q
x
Q
n
Q
n+1
Q
n+2
Q
n+3
A
n
t
SAD
t
HAD
t
SCN
t
HCN
t
DC
t
CD1
COUNTER HOLD
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
CLK
ADDRESS
ADS
DATA
OUT
CNTEN
Note
44. CE
0
and OE = V
IL
; CE
1
, R/W and CNTRST = V
IH
.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

CY7C09389V-7AXC

Mfr. #:
Buy CY7C09389V-7AXC
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 1.152M PARALLEL 100TQFP
Lifecycle:
New from this manufacturer.
Delivery:
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