CY7C09269V/79V/89V
CY7C09369V/89V
Document Number: 38-06056 Rev. *M Page 6 of 25
Functional Overview
The CY7C09269V/79V/89V and CY7C09369V/89V are high
speed 3.3 V synchronous CMOS 16K, 32K, and 64K × 16 and
16K and 64K × 18 dual-port static RAMs. Two ports are provided,
permitting independent, simultaneous access for reads and
writes to any location in memory
[11]
. Registers on control,
address, and data lines allow for minimal setup and hold times.
In pipelined output mode, data is registered for decreased cycle
time and clock to data valid t
CD2
= 7.5 ns
[12]
(pipelined). Flow
through mode can also be used to bypass the pipelined output
register to eliminate access latency. In flow through mode, data
is available t
CD1
= 18 ns after the address is clocked into the
device. Pipelined output or flow through mode is selected
through the FT/Pipe pin.
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the LOW to HIGH
transition of the clock signal. The internal write pulse is self timed
to allow the shortest possible cycle times.
A HIGH on CE
0
or LOW on CE
1
for one clock cycle powers down
the internal circuitry to reduce the static power consumption. The
use of multiple Chip Enables enables easier banking of multiple
chips for depth expansion configurations. In the pipelined mode,
one cycle is required with CE
0
LOW and CE
1
HIGH to reactivate
the outputs.
Counter enable inputs are provided to stall the operation of the
address input and use the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS
). When the port’s Count Enable (CNTEN) is asserted, the
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This reads/writes one word from or into
each successive address location, until CNTEN
is deasserted.
The counter can address the entire memory array and loop back
to the start. Counter Reset (CNTRST
) is used to reset the burst
counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Notes
11. When writing simultaneously to the same location, the final value cannot be guaranteed.
12. See Figure 4 on page 8 for Load Conditions.
