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CY7C09389V-7AXC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
CY7C09269V/79V/89V
CY7C09369V/89V
Document Number: 38-06056 Rev. *M Page 7 of 25
Maximum Ratings
Exceeding maximum ratings
[13]
may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature 65 C to +150 °C
Ambient Temperature
with Power Applied 55 C to +125 C
Supply Voltage to Ground Potential  0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State  0.5 V to V
CC
+ 0.5 V
DC Input Voltage  0.5 V to V
CC
+ 0.5 V
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 1100 V
Latch up Current ....................................................> 200 mA
Operating Range
Range Ambient Temperature V
CC
Commercial 0 °C to +70 °C 3.3 V 300 mV
Industrial –40 °C to +85 °C 3.3 V 300 mV
Electrical Characteristics
Over the Operating Range
Parameter Description
CY7C09269V/79V/89V
CY7C09369V/89V
Unit
-7
[14]
-9 -12
Min Typ Max Min Typ Max Min Typ Max
V
OH
Output HIGH Voltage (V
CC
= Min, l
OH
= –4.0 mA) 2.4 – – 2.4 – – 2.4 – – V
V
OL
Output LOW Voltage (V
CC
= Min, l
OH
= +4.0 mA) – – 0.4 – – 0.4 – – 0.4 V
V
IH
Input HIGH Voltage 2.0 – – 2.0 – – 2.0 – – V
V
IL
Input LOW Voltage – – 0.8 – – 0.8 – – 0.8 V
I
OZ
Output Leakage Current –10 – 10 –10 – 10 –10 – 10 A
I
CC
Operating Current
(V
CC
= Max, I
OUT
= 0 mA)
Outputs Disabled
Commercial – 155 275 – 135 230 – 115 180 mA
Industrial – 275 390 – 185 300 – – – mA
I
SB1
Standby Current
(Both Ports TTL Level)
[15]
CE
L
& CE
R
V
IH
, f = f
MAX
Commercial–2585–2075–2070mA
Industrial – 85 120 – 35 85 – – – mA
I
SB2
Standby Current
(One Port TTL Level)
[15]
CE
L
| CE
R
V
IH
, f = f
MAX
Commercial – 105 165 – 95 155 – 85 140 mA
Industrial – 165 210 – 105 165 – – – mA
I
SB3
Standby Current
(Both Ports CMOS Level)
[15]
CE
L
& CE
R
V
CC
– 0.2 V, f = 0
Commercial – 10 250 – 10 250 – 10 250 A
Industrial – 10 250 – 10 250 – – – A
I
SB4
Standby Current
(One Port CMOS Level)
[15]
CE
L
| CE
R
V
IH
, f = f
MAX
Commercial – 95 125 – 85 115 – 75 100 mA
Industrial – 125 170 – 95 125 – – – mA
Capacitance
Parameter
[16]
Description Test Conditions Max Unit
C
IN
Input Capacitance T
A
= 25 C, f = 1 MHz, V
CC
= 3.3 V 10 pF
C
OUT
Output Capacitance 10 pF
Notes
13. The voltage on any input or I/O pin can not exceed the power pin during power up.
14. See Figure 4 on page 8 for Load Conditions.
15. CE
L
and CE
R
are internal signals. To select either the left or right port, both CE
0
and CE
1
must be asserted to their active states (CE
0
V
IL
and CE
1
V
IH
).
16. Tested initially and after any design or process changes that may affect these parameters.
CY7C09269V/79V/89V
CY7C09369V/89V
Document Number: 38-06056 Rev. *M Page 8 of 25
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
Figure 4. AC Test Loads (Applicable to -7 only)
[17]
(a) Normal Load (Load 1)
R1 = 590
3.3 V
OUTPUT
R2 = 435
C= 30
pF
V
TH
= 1.4 V
OUTPUT
C=
30 pF
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay(Load 2)
R1 = 590
R2 = 435
3.3 V
OUTPUT
C= 5pF
R
TH
=250
(Used for t
CKLZ
, t
OLZ
, and t
OHZ
including scope and jig)
V
TH
= 1.4 V
OUTPUT
C
(a) Load 1 (-7 only)
R = 50
Z
0
= 50
3.0 V
GND
90%
90%
10%
3ns
3
ns
10%
ALL INPUTPULSES
0.00
0.1 0
0.20
0.30
0.40
0.50
0.60
530352025101
(b) Load Derating Curve
Capacitance (pF)
Δ
(ns) for all -7 access times
Note
17. Test Conditions: C = 10 pF.
CY7C09269V/79V/89V
CY7C09369V/89V
Document Number: 38-06056 Rev. *M Page 9 of 25
Switching Characteristics
Over the Operating Range
Parameter Description
CY7C09269V/79V/89V
CY7C09369V/89V
Unit
-7
[18]
-9 -12
Min Max Min Max Min Max
f
MAX1
f
Max
Flow Through –45–40–33MHz
f
MAX2
f
Max
Pipelined – 83 – 67 – 50 MHz
t
CYC1
Clock Cycle Time - Flow Through 22–25–30–ns
t
CYC2
Clock Cycle Time - Pipelined 12–15–20–ns
t
CH1
Clock HIGH Time - Flow Through 7.5 – 12 – 12 – ns
t
CL1
Clock LOW Time - Flow Through 7.5–12–12–ns
t
CH2
Clock HIGH Time - Pipelined 5 – 6 – 8 – ns
t
CL2
Clock LOW Time - Pipelined 5 – 6 – 8 – ns
t
R
Clock Rise Time –3–3–3ns
t
F
Clock Fall Time – 3 – 3 – 3 ns
t
SA
Address Set-Up Time 4–4–4–ns
t
HA
Address Hold Time 0–1–1–ns
t
SC
Chip Enable Setup Time 4 – 4 – 4 – ns
t
HC
Chip Enable Hold Time 0 – 1 – 1 – ns
t
SW
R/W Set-Up Time 4–4–4–ns
t
HW
R/W Hold Time 0–1–1–ns
t
SD
Input Data Setup Time 4 – 4 – 4 – ns
t
HD
Input Data Hold Time 0 – 1 – 1 – ns
t
SAD
ADS Set-Up Time
4–4–4–ns
t
HAD
ADS Hold Time
0–1–1–ns
t
SCN
CNTEN Setup Time
4.5 – 5 – 5 – ns
t
HCN
CNTEN Hold Time
0–1–1–ns
t
SRST
CNTRST Setup Time
4–4–4–ns
t
HRST
CNTRST Hold Time
0–1–1–ns
t
OE
Output Enable to Data Valid
–9–10–12ns
t
OLZ
[19, 20]
OE to Low Z
2–2–2–ns
t
OHZ
[19, 20]
OE to High Z
171717ns
t
CD1
Clock to Data Valid - Flow Through – 18 – 20 – 25 ns
t
CD2
Clock to Data Valid - Pipelined – 7.5 – 9 – 12 ns
t
DC
Data Output Hold After Clock HIGH 2 – 2 – 2 – ns
t
CKHZ
[19, 20]
Clock HIGH to Output High Z 2 9 2 9 2 9 ns
t
CKLZ
[19, 20]
Clock HIGH to Output Low Z 2 – 2 – 2 – ns
Port to Port Delays
t
CWDD
Write Port Clock HIGH to Read Data Delay – 35 – 40 – 40 ns
t
CCS
Clock to Clock Setup Time – 10 – 15 – 15 ns
Notes
18. See Figure 4 on page 8 for Load Conditions.
19. Test conditions used are Load 2.
20. This parameter is guaranteed by design, but it is not production tested.
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CY7C09389V-7AXC

Mfr. #:
Buy CY7C09389V-7AXC
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 1.152M PARALLEL 100TQFP
Lifecycle:
New from this manufacturer.
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