PCA8551ATT/AJ Datasheet PCA8551ATT/AJ, PCA8551BTT/AJ | P10-P12

Product data sheet Rev. 2 — 24 March 2015 10 of 57

NXP Semiconductors

PCA8551

Automotive 36 × 4 LCD segment driver

8.2.3 Command: Display_ctrl_2

[1] Default value.

8.2.3.1 Blinking

The whole display blinks at frequencies selected by the blink control bits BL[1:0], see

Table 8

. The blink frequencies are derived from the clock frequency. During the blank-out

phase of the blinking period, the display is turned off.

If an external clock with frequency f

clk(ext)

is used, the blinking frequency is determined by

Equation 1

. For notation, see Section 9.2.

(1)

8.2.3.2 Line inversion (driving scheme A) and frame inversion (driving scheme B)

The waveforms used to drive LCD inherently produce a DC voltage across the display

cell. The PCA8551 compensates for the DC voltage by inverting the waveforms on

alternate frames or alternate lines. The choice of compensation method is determined

with the INV bit.

8.3 Starting and resetting the PCA8551

If the internal Power-On Reset (POR) is enabled by connecting pin PORE to V

, the chip

resets automatically when V

rises above the minimum supply voltage. No further action

is required.

If the internal POR is disabled by connecting pin PORE to V

, the chip must be reset by

driving the RST

pin (PCA8551A only) to logic 0 for at least 10 s, see Figure 6.

Table 8. Display_ctrl_2 - display control command 2 register (address 03h) bit description

Bit Symbol Value Description

7 to 3 - 00000 default value

2 to 1 BL[1:0] blink control

[1]

blinking off

01 blinking on, f

blink

=0.5Hz

10 blinking on, f

blink

=1Hz

11 blinking on, f

blink

=2Hz

0INV inversion mode selection

[1]

line inversion (driving scheme A)

1 frame inversion (driving scheme B)

blink eff

MUX

 f

blink



clk ext

-----------------------------------------------------

Product data sheet Rev. 2 — 24 March 2015 11 of 57

NXP Semiconductors

PCA8551

Automotive 36 × 4 LCD segment driver

Alternatively a software reset can be applied (see Section 8.3.4).

Following a reset, the register 00h has to be rewritten with 0h by the next command byte

or the address pointer AP[4:0] has to be set to the required address after a new START

procedure.

8.3.1 Power-down mode

After a reset, the PCA8551 remains in power-down mode. In power-down mode the

oscillator is switched off and there is no output on pin CLK. The register settings remain

unchanged and the bus remains active. To enable the PCA8551, bit DE (command

Display_ctrl_1, see Table 7 on page 9

) must be set to logic 1.

8.3.2 Power-On Reset (POR)

If pin PORE is connected to V

, the PCA8551 comprises an internal POR, which puts

the device into the following starting conditions:

• All backplane and segment outputs are set to V

• The selected drive mode is: 1:4 multiplex with

⁄

bias

• Blinking is switched off

• The address pointer is cleared (set to logic 0)

• The display and the internal oscillator are disabled

• The display registers are set to logic 0

Remark: The internal POR can be disabled by connecting pin PORE to V

. In this case,

the internal registers are not defined and require a hardware reset according to

Section 8.3.3

or a software reset, see Section 8.3.4.

Remark: For power-on with a slowly starting power supply, see Section 16.1 on page 40

8.3.3 Hardware reset: RST pin (only PCA8551A)

At power-on the PCA8551A can be reset to the following starting conditions by pulling pin

RST

low:

• All backplane and segment outputs are set to V

Fig 6. Reset pulse timing

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Product data sheet Rev. 2 — 24 March 2015 12 of 57

NXP Semiconductors

PCA8551

Automotive 36 × 4 LCD segment driver

• The selected drive mode is: 1:4 multiplex with

⁄

bias

• Blinking is switched off

• The bus interface is initialized

• The address pointer is cleared (set to logic 0)

• The display and the internal oscillator are disabled

• The display registers are set to logic 0

Remark: The hardware reset overrides the POR see Section 8.3.2

8.3.4 Command: Software_reset

The internal registers including the display registers and the address pointer (set to

logic 0) of the device are reset by the Software_reset command.

[1] Software_reset only generates a reset pulse, therefore this register always reads back as 00h.

[2] Default value.

8.4 Display data register mapping

The example in Table 10 and Figure 7 illustrates the segment and backplane mapping of

the display in relation to the display RAM.

For example, in 1:4 multiplex drive mode, the backplanes are served by signals COM0 to

COM3 and the segments are driven by signals SEG0 to SEG35. Contents of addresses

04h to 08h are allocated to the first row (COM0) starting with the LSB driving the leftmost

element and moving forward to the right with increasing bit position. If a bit is logic 0, the

element is off, if it is logic 1 the element is turned on. All register content is LSB to MSB

left to right. Addresses 09h to 0Dh serve COM1 signals, addresses 0Eh to 12h serve

COM2 signals, and addresses 13h to 17h serve COM3 signals.

For displays with fewer segments/elements the unused bits are ignored.

Table 9. Software_reset - software reset command register (address 00h) bit description

Bit Symbol Value Description

7 to 0 SR[7:0]

[1]

software reset

00000000

[2]

no reset

00101100 software reset

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57

PCA8551ATT/AJ

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Flip Flops Automotive 36X4 LCD segment driver

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