PCA8551ATT/AJ Datasheet PCA8551ATT/AJ, PCA8551BTT/AJ | P7-P9

Product data sheet Rev. 2 — 24 March 2015 7 of 57

NXP Semiconductors

PCA8551

Automotive 36 × 4 LCD segment driver

8. Functional description

8.1 Registers of the PCA8551

The registers of the PCA8551 are arranged in bytes with 8 bit, addressed by an address

pointer. Table 5

depicts the layout.

For writing to the registers, send the address byte first, then write the data to the register

(see Section 11.1.4

and Section 11.2.1). The address byte works as an address pointer.

For the succeeding registers, the address pointer is automatically incremented by 1 (see

Figure 5

) and all following data are written into these register addresses. After register

18h, the auto-incrementing will stop and subsequent data are ignored.

Table 5. Registers of the PCA8551

Bits labeled as 0 must always be written with logic 0; bits labeled as - are ignored by the device.

AP[4:0] 7 6 5 4 3 2 1 0

Command registers

Software_reset 00h SR[7:0] Table 9

Device_ctrl 01h 0 0 0 FF[2:0] OSC COE Ta bl e 6

Display_ctrl_1 02h 0 0 0 BOOST MUX[1:0] B DE Table 7

Display_ctrl_203h00000BL[1:0] INVTable 8

Display data registers

COM0 04h SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 Table 10

05h SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8

06h SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16

07h SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24

08h - - - - SEG35 SEG34 SEG33 SEG32

COM1

09h SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0

0Ah SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8

0Bh SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16

0Ch SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24

0Dh - - - - SEG35 SEG34 SEG33 SEG32

COM2 0Eh SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0

0Fh SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8

10h SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16

11h SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24

12h - - - - SEG35 SEG34 SEG33 SEG32

COM3 13h SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0

14h SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8

15h SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16

16h SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24

17h - - - - SEG35 SEG34 SEG33 SEG32

Product data sheet Rev. 2 — 24 March 2015 8 of 57

NXP Semiconductors

PCA8551

Automotive 36 × 4 LCD segment driver

8.2 Command registers of the PCA8551

8.2.1 Command: Device_ctrl

The Device_ctrl command sets the device into a defined state. It should be executed

before enabling the display (see bit DE in Table 7

[1] Default value.

8.2.1.1 Internal oscillator and clock output

Bit OSC enables or disables the internal oscillator. When the internal oscillator is used, bit

COE allows making the clock signal available on pin CLK. If this is not intended, pin CLK

should be left open. The design ensures that the duty cycle of the clock output is 50 : 50

(% HIGH-level time : % LOW-level time).

Fig 5. Address counter incrementing

DDD

DGGUHVVFRXQWHU

K

DXWRLQFUHPHQW

K

K

K



K

K

K

Table 6. Device_ctrl - device control command register (address 01h) bit description

Bit Symbol Value Description

7 to 5 - 000 default value

4 to 2 FF[2:0] frame frequency selection

000 f

=32Hz

001

[1]

=64Hz

010 f

=96Hz

011 f

=128Hz

100 f

=160Hz

101 f

=192Hz

110 f

=224Hz

111 f

=256Hz

1OSC internal oscillator control

[1]

enabled

1disabled

0COE clock output enable

[1]

clock signal not available on pin CLK; pin CLK is in

3-state

1 clock signal available on pin CLK

Product data sheet Rev. 2 — 24 March 2015 9 of 57

NXP Semiconductors

PCA8551

Automotive 36 × 4 LCD segment driver

In applications where an external clock has to be applied to the PCA8551, bit OSC must

be set logic 1 and COE logic 0. In this case pin CLK becomes an input.

In power-down mode (see Section 8.3.1

)

• if pin CLK is configured as an output, there is no signal on CLK

• if pin CLK is configured as an input, the signal on CLK can be removed.

Remark: A clock signal must always be supplied to the device if the display is enabled

(see bit DE in Table 7 on page 9

). Removing the clock may freeze the LCD in a DC state,

which is not suitable for the liquid crystal.

8.2.2 Command: Display_ctrl_1

The Display_ctrl_1 command allows configuring the basic display set-up.

[1] Default value.

[2] Not applicable for static drive mode.

[3] See Section 8.3.1

8.2.2.1 Enhanced power drive mode

By setting the BOOST bit to logic 1, the driving capability of the display signals is

increased to cope with large displays with a higher effective capacitance. Setting this bit

increases the current consumption on V

LCD

8.2.2.2 Multiplex drive mode

MUX[1:0] sets the multiplex driving scheme and the associated backplane drive signals,

which are active. For further details, see Section 9.2 on page 17

Table 7. Display_ctrl_1 - display control command 1 register (address 02h) bit description

Bit Symbol Value Description

7 to 5 - 000 default value

4BOOST large display mode support

[1]

standard power drive scheme

1 enhanced power drive scheme for higher display

loads

3 to 2 MUX[1:0] multiplex drive mode selection

[1]

1:4 multiplex drive mode; COM0 to COM3

MUX

=4)

01 1:3 multiplex drive mode; COM0 to COM2

MUX

=3)

10 1:2 multiplex drive mode; COM0 and COM1

MUX

=2)

11 static drive mode; COM0 (n

MUX

=1)

[2]

bias mode selection

[1] 1

⁄

bias (a

bias

=2)

⁄

bias (a

bias

=1)

0DE display enable

[3]

[1]

display disabled; device is in power-down mode

1 display enabled; device is in power-on mode

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57

PCA8551ATT/AJ

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NXP Semiconductors

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Flip Flops Automotive 36X4 LCD segment driver

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PCA8551ATT/AJ

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