PCA8551ATT/AJ Datasheet PCA8551ATT/AJ, PCA8551BTT/AJ | P28-P30

Product data sheet Rev. 2 — 24 March 2015 28 of 57

NXP Semiconductors

PCA8551

Automotive 36 × 4 LCD segment driver

11.1.2 START and STOP conditions

A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START

condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P (see Figure 19

11.1.3 Acknowledge

Each byte of 8 bits is followed by an acknowledge cycle. An acknowledge is defined as

logic 0. A not-acknowledge is defined as logic 1.

When written to, the slave will generate an acknowledge after the reception of each byte.

After the acknowledge, another byte may be transmitted. It is also possible to send a

STOP or START condition.

When read from, the master receiver must generate an acknowledge after the reception

of each byte. When the master receiver no longer requires bytes to be transmitted, it must

generate a not-acknowledge. After the not-acknowledge, either a STOP or START

condition must be sent.

Remark: The PCA8551A omits the not-acknowledge. After the last byte read, the end of

transmission is indicated by a STOP or START condition from the master.

A detailed description of the I

C-bus specification is given in Ref. 12 “UM10204”.

11.1.4 I

C interface protocol

The PCA8551A uses the I

C interface for data transfer. Interpretation of the data is

determined by the interface protocol.

11.1.4.1 Write protocol

After the I

C slave address is transmitted, the PCA8551A requires that the register

address pointer is defined. It can take the value 00h to 17h. Values outside of that range

will result in the transfer being ignored, however the slave will still respond with

acknowledge pulses.

After the register address has been transmitted, write data is transmitted. The minimum

number of data write bytes is 0 and the maximum number is unlimited. After each write,

the address pointer increments by one. After address 17h, the address pointer stops

incrementing at 18h.

• I

C START condition

• I

C slave address + write

• start register pointer

• write data

• :

• write data

• I

C STOP condition; an I

C RE-START condition is also possible.

Product data sheet Rev. 2 — 24 March 2015 29 of 57

NXP Semiconductors

PCA8551

Automotive 36 × 4 LCD segment driver

11.1.4.2 Read protocol

When reading the PCA8551A, reading starts at the current position of the address pointer.

The address pointer for read data should first be defined by a write sequence.

• I

C START condition

• I

C slave address + write

• start address pointer

• I

C STOP condition; an I

C RE-START condition is also possible.

After setting the address pointer, a read can be executed. After the I

C slave address is

transmitted, the PCA8551A will immediately output read data. After each read, the

address pointer increments by one. After address 17h, the address pointer stops

incrementing at 18h.

• I

C START condition

• I

C slave address + read

• read data (master sends acknowledge bit)

• :

11.1.4.3 I

C-bus slave address

Device selection depends on the I

C-bus slave address (see Table 13).

The least significant bit of the slave address byte is bit R/W (see Table 14).

Table 13. I

C slave address byte

Slave address

Bit 7

MSB

6 5 4 3 2 1 0

LSB

0111000R/W

Table 14. R/W-bit description

R/W Description

0 write data

1 read data

Product data sheet Rev. 2 — 24 March 2015 30 of 57

NXP Semiconductors

PCA8551

Automotive 36 × 4 LCD segment driver

11.2 SPI-bus interface of the PCA8551B

Data transfer to the device is made via a 3-line SPI-bus (see Table 15). There is no

dedicated output data line. The SPI-bus is initialized whenever the chip enable line pin CE

is pulled down.

[1] The chip enable must not be wired permanently LOW.

11.2.1 Data transmission

The chip enable signal is used to identify the transmitted data. Each data transfer is a byte

with the Most Significant Bit (MSB) sent first.

The transmission is controlled by the active LOW chip enable signal CE

. The first byte

transmitted is the register address comprising of the address pointer and the R/W

bit.

After the register address byte, the register contents follows with the address pointer

being auto-incremented after every eighth bit sent (see Section 8.1 on page 7

11.2.1.1 Write protocol

After the CE

is set LOW, the PCA8551B requires that R/W and the register address

pointer is defined. It can take the value 00h to 17h. Values outside of that range will result

in the transfer being ignored.

After the register address has been transmitted, write data is transmitted. The minimum

number of data write bytes is 0 and the maximum number is unlimited. After each write,

the address pointer increments by one. After address 17h, the address pointer stops

incrementing at 18h.

Table 15. Serial interface

Symbol Function Description

chip enable input

[1]

; active LOW when HIGH, the interface is reset

SCL serial clock input input may be higher than V

SDIO serial data input/output input data are sampled on the rising edge of SCL,

output data are valid after the falling edge of SCL

Fig 20. Data transfer overview

Table 16. Address byte definition

Bit Symbol Value Description

7R/W

data read or write selection

0 write data

1 read data

6 to 5 - 00 default value

4to0 AP[4:0] pointer to register start address

00h to 17h valid range; other addresses are ignored

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PCA8551ATT/AJ

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Flip Flops Automotive 36X4 LCD segment driver

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PCA8551ATT/AJ

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