PCA8551 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 24 March 2015 37 of 57
NXP Semiconductors
PCA8551
Automotive 36 × 4 LCD segment driver
(1) n
MUX
=1.
(2) n
MUX
=2.
(3) n
MUX
=3.
(4) n
MUX
=4.
Fig 27. Relation of frame frequency (f
fr
), clock frequency (f
clk
) and multiplex-rate (n
MUX
)
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PCA8551 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 24 March 2015 38 of 57
NXP Semiconductors
PCA8551
Automotive 36 × 4 LCD segment driver
[1] The I
2
C-bus interface of PCA8551A is 5 V tolerant.
Table 20. I
2
C-bus characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; T
amb
=
40
C to +105
C; unless otherwise specified; all timing values are valid within the
operating supply voltage and T
amb
range and are referenced to V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
.
[1]
Symbol Parameter Conditions Min Typ Max Unit
Pin SCL
f
SCL
SCL clock frequency - - 400 kHz
t
LOW
LOW period of the SCL
clock
1.3 - - s
t
HIGH
HIGH period of the SCL
clock
0.6 - - s
Pin SDA
t
SU;DAT
data set-up time 100 - - ns
t
HD;DAT
data hold time 0 - - ns
Pins SCL and SDA
t
BUF
bus free time between a
STOP and START
condition
1.3 - - s
t
SU;STO
set-up time for STOP
condition
0.6 - - s
t
HD;STA
hold time (repeated)
START condition
0.6 - - s
t
SU;STA
set-up time for a repeated
START condition
0.6 - - s
t
r
rise time of both SDA and
SCL signals
f
SCL
= 400 kHz - - 0.3 s
t
f
fall time of both SDA and
SCL signals
--0.3s
C
b
capacitive load for each
bus line
--400pF
t
w(spike)
spike pulse width on the I
2
C-bus - - 50 ns
PCA8551 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 24 March 2015 39 of 57
NXP Semiconductors
PCA8551
Automotive 36 × 4 LCD segment driver
Fig 28. I
2
C-bus timing waveforms
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Table 21. SPI-bus characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; T
amb
=
40
C to +105
C; unless otherwise specified; all timing values are valid within the
operating supply voltage and T
amb
range and are referenced to V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
.
Symbol Parameter Conditions Min Typ Max Unit
Pin SCL
f
SCL
SCL clock frequency - - 5 MHz
t
LOW
LOW period of the SCL
clock
150 - - ns
t
HIGH
HIGH period of the SCL
clock
80 - - ns
t
r
rise time - - 100 ns
t
f
fall time - - 100 ns
Pin CE
t
su(CE_N)
CE_N set-up time 30 - - ns
t
h(CE_N)
CE_N hold time 10 - - ns
t
rec(CE_N)
CE_N recovery time 70 - - ns
Pin SDIO
t
su
set-up time write data 5 - - ns
t
h
hold time write data 50 - - ns
t
d(R)SDIO
SDIO read delay time C
L
= 50 pF - - 150 ns
t
dis(SDIO)
SDIO disable time no load - - 50 ns
t
t(SDI-SDO)
transition time from SDI to
SDO
write to read mode 0 - - ns

PCA8551ATT/AJ

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Flip Flops Automotive 36X4 LCD segment driver
Lifecycle:
New from this manufacturer.
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