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PCA8551ATT/AJ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57
PCA8551 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 24 March 2015 25 of 57
NXP Semiconductors
PCA8551
Automotive 36 × 4 LCD segment driver
9.3 Backplane and segment outputs
9.3.1 Backplane outputs
The LCD drive section includes four backplane outputs COM0 to COM3, which must be
directly connected to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-circuit.
• In 1:3 multiplex drive mode, COM3 carries the same signal as COM1, therefore these
two outputs can be tied together to give enhanced drive capabilities
• In 1:2 multiplex drive mode, COM0 and COM2, respectively, COM1 and COM3 all
carry the same signals and may also be paired to increase the drive capabilities
• In static drive mode, the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements
9.3.2 Segment outputs
The LCD drive section includes 36 segment outputs SEG0 to SEG35, which must be
directly connected to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display registers.
When less than 36 segment outputs are required, the unused segment outputs must be
left open-circuit.
PCA8551 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 24 March 2015 26 of 57
NXP Semiconductors
PCA8551
Automotive 36 × 4 LCD segment driver
10. Power Sequencing
10.1 Power-on
To avoid unwanted artifacts on the display, V
LCD
must never be asserted before V
DD
, it is
permitted to assert V
DD
and V
LCD
at the same time.
10.2 Power-off
Before turning the power to the device off, the display must be disabled by setting bit DE
to logic 0. To avoid unwanted artifacts on the display, V
LCD
must never be connected,
while V
DD
is switched off. It is permitted to switch off V
DD
and V
LCD
simultaneously.
10.3 Power sequences
Figure 17 depicts the recommended power-up and power-off sequence.
Reset: internal power-on reset if PORE = 1, or software reset. If an external oscillator is used, clock
must be available after reset.
(1) Can be simultaneous with V
DD
.
(2) Can be simultaneous with V
LCD
.
Fig 17. Recommended power-up and power-off sequence
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PCA8551 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 24 March 2015 27 of 57
NXP Semiconductors
PCA8551
Automotive 36 × 4 LCD segment driver
11. Bus interfaces
11.1 I
2
C-bus interface of the PCA8551A
The I
2
C-bus is for bidirectional, two-line communication between different ICs. The two
lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy. Both data and clock lines remain HIGH when the bus is not
busy. The PCA8551A acts as a slave receiver when being written to and as a slave
transmitter when being read from.
11.1.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse, as changes in the data line at this time
are interpreted as STOP or START conditions.
Fig 18. I
2
C read and write protocol
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57

PCA8551ATT/AJ

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Buy PCA8551ATT/AJ
Manufacturer:
NXP Semiconductors
Description:
Flip Flops Automotive 36X4 LCD segment driver
Lifecycle:
New from this manufacturer.
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