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MT9J003I12STMUH-GEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55
MT9J003
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10
OUTPUT DATA FORMAT
Serial Pixel Data Interface
The MT9J003 supports RAW8, RAW10, and RAW12
image data formats over a serial interface. The sensor
supports a 1 and 2-lane MIPI as well as the HiSPi interface.
These interfaces are not described in the data sheet.
High Speed Serial Pixel Interface
The High Speed Serial Pixel (HiSPi) interface uses four
data and one clock low voltage differential signaling
(LVDS) outputs.
• SLVS_CP, SLVS_CN
• SLVS_[0:3]P, SLVS_[0:3]N
The HiSPi interface supports two protocols, streaming
and packetized. The streaming protocol conforms to a
standard video application where each line of active or
intra-frame blanking provided by the sensor is transmitted
at the same length. The packetized protocol will transmit
only the active data ignoring line-to-line and frame-to-frame
blanking data.
The HiSPi interface building block is a unidirectional
differential serial interface with four data and one double
data rate (DDR) clock lanes. One clock for every four serial
data lanes is provided for phase alignment across multiple
lanes. Figure 7 shows the configuration between the HiSPi
transmitter and the receiver.
Figure 7. HiSPi Transmitter and Receiver Interface Block Diagram
A camera containing
the HiSPi transmitter
A host (DSP) containing
the HiSPi receiver
Dp0
Dn0
Dp1
Dn1
Dp2
Dn2
Dp3
Dn3
Cp0
Cn0
Tx
PHY0
Rx
PHY0
Dp0
Dn0
Dp1
Dn1
Dp2
Dn2
Dp3
Dn3
Cp0
Cn0
HiSPi Physical Layer
The HiSPi physical layer is partitioned into blocks of four
data lanes and an associated clock lane. Any reference to the
PHY in the remainder of this document is referring to this
minimum building block.
The PHY will serialize a 10-, 12-, 14- or 16-bit data word
and transmit each bit of data centered on a rising edge of the
clock, the second on the following edge of clock. Figure 8
shows bit transmission. In this example, the word is
transmitted in order of MSB to LSB. The receiver latches
data at the rising and falling edge of the clock.
Figure 8. Timing Diagram
cp
dn
…
…
MSB
LSB
TxPost
dp
cn
1 UI
TxPre
MT9J003
www.onsemi.com
11
DLL Timing Adjustment
The specification includes a DLL to compensate for
differences in group delay for each data lane. The DLL is
connected to the clock lane and each data lane, which acts as
a control master for the output delay buffers. Once the DLL
has gained phase lock, each lane can be delayed in 1/8 unit
interval (UI) steps. This additional delay allows the user to
increase the setup or hold time at the receiver circuits and
can be used to compensate for skew introduced in PCB
design.
If the DLL timing adjustment is not required, the data and
clock lane delay settings should be set to a default code of
0x000 to reduce jitter, skew, and power dissipation.
Figure 9. Block Diagram of DLL Timing Adjustment
delay
del 0[2: 0]
delay
del 1[2: 0]
delay delay
del 3[2: 0]
delay
del 2[2: 0]
data _lane 0 data _lane 1 clock_lane0
delclock[2:0]
data_lane2 data_lane3
Figure 10. Delaying the clock_lane with Respect to data_lane
increasing delclock_[2:0] increases clock delay
1 UI
cp (delclock = 000)
cp (delclock = 001)
cp (delclock = 010)
cp (delclock = 011)
cp (delclock = 100)
cp (delclock = 101)
cp (delclock = 110)
cp (delclock = 111)
dataN (de IN = 000)
Figure 11. Delaying data_lane with Respect to the clock_lane
1 UI
t
DLLSTEP
increasing delN_[2:0] increases data delay
dataN (delN = 000)
dataN (delN = 001)
dataN (delN = 010)
dataN (delN = 011)
dataN (delN = 100)
dataN (delN = 101)
dataN (delN = 110)
dataN (delN = 111)
cp (delclock = 000)
MT9J003
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12
HiSPi Streaming Mode Protocol Layer
The protocol layer is positioned between the output data
path of the sensor and the physical layer. The main functions
of the protocol layer are generating sync codes, formatting
pixel data, inserting horizontal/vertical blanking codes, and
distributing pixel data over defined data lanes.
The HiSPi interface can only be configured when the
sensor is in standby. This includes configuring the interface
to transmit across 1, 2, or all 4 data lanes.
Protocol Fundamentals
Referring to Figure 12, it can be seen that a SYNC code
is inserted in the serial data stream prior to each line of image
data. The streaming protocol will insert a SYNC code to
transmit each active data line and vertical blanking lines.
The packetized protocol will transmit a SYNC code to
note the start and end of each row. The packetized protocol
uses sync a “Start of Frame” (SOF) sync code at the start of
a frame and a “Start of Line” (SOL) sync code at the start of
a line within the frame. The protocol will also transmit an
“End of Frame” (EOF) at the end of a frame and an “End of
Line” (EOL) sync code at the end of a row within the frame
Figure 12. Steaming vs. Packetized Transmission
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MT9J003I12STMUH-GEVB

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Manufacturer:
ON Semiconductor
Description:
Optical Sensor Development Tools 10 MP NAVITAR
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