MT9J003
www.onsemi.com
44
TIMING SPECIFICATIONS
Power-Up Sequence
The recommended power-up sequence for the MT9J003
is shown in Figure 45. The available power supplies−
V
DD_IO, VDD, VDD_TX, VDD_PLL, VAA, VAA_PIX,
VDD_SLVS, VDD_SLVS_TX− can be turned on at the same time
or have the separation specified below.
1. Turn on V
DD_IO power supply.
2. After 1–500 ms, turn on V
DD and VDD_TX power
supply.
3. After 1–500 ms, turn on V
DD_PLL and
V
AA/VAA_PIX power supplies.
4. After the last power supply is stable, enable
EXTCLK.
5. Assert RESET_BAR for at least 1ms.
6. Wait 2400 EXTCLKs for internal initialization
into software standby.
7. Configure PLL, output, and image settings to
desired values
8. Set mode_select = 1 (R0x0100).
9. Wait 1 ms for the PLL to lock before streaming
state is reached.
Figure 45. Power−Up Sequence
Internal
INIT
Hard
Reset
Software
Standby
PLL
Lock Streaming
t
1
t
2
t
3
t
5
t
6
t
7
V
DD
_SLVS_TX
t
4
V
AA
, VAA_PIX
EXTCLK
V
DD
_PLL
V
DD
_IO
RESET_BAR
V
DD
, V
DD
_SLVS, V
DD
_TX
Table 23. POWER-UP SEQUENCE
Definition
Symbol Min Typ Max Unit
V
DD
_IO to V
DD
, V
DD
_TX Time
t
1 0 – 500 ms
V
DD
, V
DD
_TX to V
DD
_PLL Time
t
2 0 – 500 ms
V
DD
, V
DD
_TX to V
AA
/V
AA
_PIX Time
t
3 0 – 500 ms
V
AA
, V
AA
_PIX to V
DD
_SLVS_TX
t
4 − – 500 ms
Active Hard Reset
t
5 1 – − ms
Internal Initialization
t
6 2400 – − EXTCLKs
PLL Lock Time
t
7 1 – − ms
1. Digital supplies must be turned on before analog supplies.
Power-Down Sequence
The recommended power-down sequence for the
MT9J003 is shown in Figure 46. The available power
supplies− V
DD_IO, VDD, VDD_TX0, VDD_PLL, VAA,
V
AA_PIX, VDD_SLVS, VDD_SLVS_TX− can be turned off
at the same time or have the separation specified below.
1. Disable streaming if output is active by setting
mode_select = 0 (R0x0100).
2. The soft standby state is reached after the current
row or frame, depending on configuration, has
ended.
