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MT9J003I12STMUH-GEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55
MT9J003
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49
Table 27. PARALLEL INTERFACE CONFIGURED TO USE LOW POWER MODE
(
f
EXTCLK = 15 MHz; V
DD
= 1.8 V; V
DD
_IO = 1.8 V; V
AA
= 2.8 V; VAA_PIX = 2.8 V; V
DD
_PLL = 2.8 V; T
J
= 60°C;
Parallel Data Rate = 80 Mp/s)
Frame Rate I
AA
I
DDPLL
I
DD
I
DDIO
IA
APIX
10 MP 7.5 fps 103.29 10.26 23.93 11.53 2.33 388 mW
720p60 59.94 fps 122.78 10.25 23.85 11.21 5.39 451 mW
1080p30 29.97 fps 114.67 10.26 22.89 4.49 4.14 411 mW
VGA60 59.94 fps 82.66 10.27 18.5 4.51 5.25 316 mW
Monitor 29.97 fps 69.22 10.28 16.3 6.35 2.76 271 mW
1. Monitor is a low power VGA preview mode. The power consumption values in this table represent a small sample of MT9J003 sensors. The
I
DDIO current will double if the VDD_IO voltage is raised to 2.8V.
Figure 51. Two-Wire Serial Bus Timing Parameters
S
CLK
Write Start
ACK
Stop
S
CLK
Read Start
ACK
tr_clk tf_clk
90%
10%
tr_sdat tf_sdat
90%
10%
t
SCLK
S
DATA
S
DATA
t
SRTH
t
SDH
t
SDS
t
SHAW
t
AHSW
t
SHAR
t
AHSR
t
SDHR
t
SDSR
t
STPS
t
STPH
Register
Value
Bit
7
Read
Address
Bit
0
Read
Address
Bit
7
Register
Value
Bit
0
Write
Address
Bit
0
Write
Address
Bit
7
Register
Address
Bit
7
Register
Value
Bit
0
1. Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued.
Table 28. TWO-WIRE SERIAL REGISTER INTERFACE ELECTRICAL CHARACTERISTICS
(
f
EXTCLK = 15 MHz; V
DD
= 1.8 V; V
DD
_IO = 1.8 V; V
AA
= 2.8 V; VAA_PIX = 2.8 V; V
DD
_PLL = 2.8 V; V
DD
_SLVS = 1.8 V,
VDD_SLVS_TX = 0.4 V; Output load = 68.5 pF; T
J
= 60°C; Data Rate = 480 MHz; DLL set to 0)
Symbol Parameter Condition Min Typ Max Unit
VIL Input LOW voltage –0.5 0.73 0.3 x VDD_IO V
IIN Input leakage current No pull up resistor;
V
IN = VDD_IO or DGND
–2 2 μA
VOL Output LOW voltage At specified 2 mA 0.031 0.032 0.035 V
IOL Output LOW current At specified VOL 0.1 V 3 mA
CIN Input pad capacitance 6 pF
CLOAD Load capacitance pF
MT9J003
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50
Table 29. TWO−WIRE SERIAL REGISTER INTERFACE TIMING SPECIFICATION
(
f
EXTCLK = 15 MHz; V
DD
= 1.8 V; V
DD
_IO = 1.8 V; V
AA
= 2.8V; VAA_PIX = 2.8 V; V
DD
_PLL = 2.8 V; V
DD
_SLVS = 1.8 V,
VDD_SLVS_TX = 0.4 V; Output load = 68.5 pF; T
J
= 60°C; Data Rate = 480 MHz,; DLL set to 0)
Symbol Parameter Condition Min Typ Max Unit
fSCLK Serial Interface Input Clock – 0 100 400 kHz
SCLK Duty Cycle VOD 45 50 60 %
tR SCLK/SDATA Rise Time 300 μs
tSRTS Start Setup Time Master WRITE to Slave 0.6 μs
tSRTH Start Hold Time Master WRITE to Slave 0.4 μs
tSDH SDATA Hold Master WRITE to Slave 0.3 0.65 μs
tSDS SDATA Setup Master WRITE to Slave 0.3 μs
tSHAW SDATA Hold to ACK Master READ to Slave 0.15 0.65 μs
tAHSW ACK Hold to SDATA Master WRITE to Slave 0.15 0.70 μs
tSTPS Stop Setup Time Master WRITE to Slave 0.3 μs
tSTPH Stop Hold Time Master WRITE to Slave 0.6 μs
tSHAR SDATA Hold to ACK Master WRITE to Slave 0.3 1.65 μs
tAHSR ACK Hold to SDATA Master WRITE to Slave 0.3 0.65 μs
tSDHR SDATA Hold Master READ from Slave 012 0.70 μs
tSDSR SDATA Setup Master READ from Slave 0.3 μs
Figure 52. I/O Timing Diagram
Data[11:0]
FRAME_VALID/
LINE_VALID
FRAME_VALID leads LINE_VALID by 6 PIXCLKs.
FRAME_VALID trails
LINE_VALID by 6 PIXCLKs.
PIXCLK
EXTCLK
90 %
10 %
90 %
10 %
t
PD
t
CP
t
PD
Pxl_0 Pxl_1 Pxl_2 Pxl_n
t
PFH
t
PLH
t
PFL
t
PLL
t
EXTCLK
t
R
t
F
t
RP
t
FP
MT9J003
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51
Table 30. I/O PARAMETERS
(
f
EXTCLK = 15 MHz; V
DD
= 1.8 V; V
AA
= 2.8 V; VAA_PIX = 2.8 V; V
DD
_PLL = 2.8 V; V
DD
_SLVS = 1.8 V, VDD_SLVS_TX = 0.4 V;
Output load = 68.5 pF; T
J
= 60°C; Data Rate = 480 MHz,; DLL set to 0)
Symbol
Definition Conditions Min Max Units
VIH Input HIGH Voltage
VDD_IO = 1.8V 1.4
VDD_IO
+ 0.3
V
VDD_IO = 2.8V 2.4
VIL Input LOW Voltage
VDD_IO = 1.8V GND – 0.3 0.4
VDD_IO = 2.8V GND – 0.3 0.8
IIN Input Leakage Current No Pull-up Resistor; VIN = VDD OR DGND – 20 20 μA
VOH Output HIGH Voltage At Specified IOH VDD_IO − 0.4V – V
VOL Output LOW Voltage At Specified IOL – 0.4 V
IOH Output HIGH Current At Specified VOH – –12 mA
IOL Output LOW Current At Specified VOL – 9 mA
IOZ Tri-state Output Leakage Current – 10 μA
Table 31. I/O TIMING
(
f
EXTCLK = 15 MHz; V
DD
= 1.8 V; V
DD
_IO = 1.8 V; V
AA
= 2.8 V; VAA_PIX = 2.8 V; V
DD
_PLL = 2.8 V; V
DD
_SLVS = 1.8 V, VDD_SLVS_TX
= 0.4 V; Output load = 68.5 pF; T
J
= 60°C; Data Rate = 480 MHz; DLL set to 0)
Symbol
Definition Conditions Min Typ Max Units
f
EXTCLK Input Clock Frequency PLL Enabled 6 24 48 MHz
t
EXTCLK Input Clock Period PLL Enabled 166 41 20 ns
t
R Input Clock Rise Time 0.1 – 1 V/ns
t
F Input Clock Fall Time 0.1 – 1 V/ns
Clock Duty Cycle 45 50 55 %
t
JITTER Input Clock Jitter – – 0.3 ns
Output Pin Slew Fastest CLOAD = 15 pF – 0.7 – V/ns
f
PIXCLK PIXCLK Frequency Default – 80 – MHz
t
PD PIXCLK to Data Valid Default – – 3 ns
t
PFH PIXCLK to FRAME_VALID HIGH Default – – 3 ns
t
PLH PIXCLK to LINE_VALID HIGH Default – – 3 ns
t
PFL PIXCLK to FRAME_VALID LOW Default – – 3 ns
t
PLL PIXCLK to LINE_VALID LOW Default – – 3 ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55

MT9J003I12STMUH-GEVB

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Manufacturer:
ON Semiconductor
Description:
Optical Sensor Development Tools 10 MP NAVITAR
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