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MT9J003I12STMUH-GEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55
MT9J003
www.onsemi.com
13
Parallel Pixel Data Interface
MT9J003 image data is read out in a progressive scan.
Valid image data is surrounded by horizontal blanking and
vertical blanking, as shown in Figure 13. The amount of
horizontal blanking and vertical blanking is programmable;
LV is HIGH during the shaded region of the figure. FV
timing is described in the “Output Data Timing (Parallel
Pixel Data Interface)”.
Figure 13. Spatial Illustration of Image Readout
.....................................
.....................................
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
.................................
.................................
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
VALID IMAGE
HORIZONTAL
BLANKING
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
VERTICAL BLANKING
VERTICAL/HORIZONTAL
BLANKING
P
0,0
P
0,1
P
0,2
P
1,0
P
1,1
P
1,2
P
0,n−1
P
0,n
P
1,n−1
P
1,n
P
m−1,0
P
m−1,1
P
m,0
P
m,1
P
m−1,n−1
P
m−1,n
P
m,n−1
P
m,n
Output Data Timing (Parallel Pixel Data Interface)
MT9J003 output data is synchronized with the PIXCLK
output. When LV is HIGH, one pixel value is output on the
12-bit D
OUT output every PIXCLK period. The pixel clock
frequency can be determined based on the sensor’s master
input clock and internal PLL configuration. The rising edges
on the PIXCLK signal occurs one-half of a pixel clock
period after transitions on LV, FV, and D
OUT (see Figure 14).
This allows PIXCLK to be used as a clock to sample the data.
PIXCLK is continuously enabled, even during the blanking
period. The MT9J003 can be programmed to delay the
PIXCLK edge relative to the D
OUT transitions. This can be
achieved by programming the corresponding bits in the
row_speed register. The parameters P, A, and Q in Figure 15
are defined in Table 4.
Figure 14. Pixel Data Timing Example
P
0
[11:0]
P
1
[11:0]
P
2
[11:0]
P
3
[11:0]
P
4
[11:0]
P
5n−2
P
n−1
[11:0]
P
n
[11:0]
Valid Image DataBlanking Blanking
LV
PIXCLK
DOUT[11:0]
P
MT9J003
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14
Figure 15. Row Timing and FV/LV Signals
FV
LV
Number of
master clocks
PAQ AQAP
The sensor timing (shown in Table 4) is shown in terms of
pixel clock and master clock cycles (see Figure 14). The
default settings for the on-chip PLL generate
a pixel array clock (vt_pix_clk) of 160 MHz and an output
clock (op_pix_clk) of 40 MHz given a 20 MHz input clock
to the MT9J003. Equations for calculating the frame rate are
given in “Frame Rate Control”.
Table 4. ROW TIMING WITH HiSPi INTERFACE
Parameter
Name Equation Default Timing
PIXCLK_
PERIOD
Pixel Clock Period 1/vt_pix_clk_freq_mhz 1 Pixel Clock
= 6.25 ns
S Skip (Subsampling)
Factor
For x_odd_inc = y_odd_inc = 3, S = 2.
For x_odd_inc = y_odd_inc = 7, S = 4.
otherwise, S = 1
For y_odd_inc = 3, S = 2
For y_odd_inc = 7, S = 4
For y_odd_inc = 15, S = 8
For y_odd_inc = 31, S = 16
For y_odd_inc = 63, S = 32
1
A Active Data Time (x_addr_end – x_addr_start + x_odd_inc) * 0.5 * PIXCLK_PERIOD/S
= 3775 – 112 + 12
1832 Pixel Clock
= 11.45
μs
P Frame Start/end
Blanking
6 * PIXCLK_PERIOD 6 Pixel Clock
= 37.5 ns
Q Horizontal Blanking (line_length_pck – A) * PIXCLK_PERIOD
= 3694 – 1832
1862 Pixel Clock
= 11.63
μs
A + Q Row Time line_length_pck * PIXCLK_PERIOD 3694 Pixel Clock
= 23.09
μs
N Number of Rows (y_addr_end – y_addr_start + y_odd_inc) / S = (2755 – 8 + 1)/1 2748 Rows
V Vertical Blanking ((frame_length_lines – N) * (A + Q)) + Q – (2 * P)
= (2891 – 2748) * 3694 + 1862 − 12
530092 Pixel Clock
= 3.31 ms
T Frame Valid Time (N * (A + Q)) – Q + (2 * P)
= 2748*3694 – 1862 + 12
10149262 Pixel Clock
= 63.42 ms
F Total Frame Time line_length_pck * frame_length_lines * PIXCLK_PERIOD
= 2891 * 3694
10679354 Pixel Clock
= 66.75 ms
MT9J003
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15
Table 5. ROW TIMING WITH PARALLEL INTERFACE
Parameter
Name Equation Default Timing
PIXCLK_
PERIOD
Pixel Clock Period 1/vt_pix_clk_freq_mhz 1 Pixel Clock
= 6.25 ns
S Skip (Subsampling)
Factor
For x_odd_inc = y_odd_inc = 3, S = 2.
For x_odd_inc = y_odd_inc = 7, S = 4.
otherwise, S = 1
For y_odd_inc = 3, S = 2
For y_odd_inc = 7, S = 4
For y_odd_inc = 15, S = 8
For y_odd_inc = 31, S = 16
For y_odd_inc = 63, S = 32
1
A Active Data Time (x_addr_end – x_addr_start + x_odd_inc) * 0.5 * PIXCLK_PERIOD/S
= (3775 – 112+1)/2
1832 Pixel Clocks
= 11.45
μs
P Frame Start/end
Blanking
6 * PIXCLK_PERIOD 6 Pixel Clocks
= 75 ns
Q Array Horizontal
Blanking
(line_length_pck – A) * PIXCLK_PERIOD
= 7358 – 1832
5526 Pixel Clocks
= 34.5
μs
External horizontal
blanking is 30 pixel
clocks or 187 ns.
A + Q Row Time Limited by
Output Interface
Speed
x_output_size * clk_pixel/clk_op + 30
= 3664 * 160 MHz/80 MHz + 30
7358 Pixel Clocks
= 46.1
μs
N Number of Rows (y_addr_end − y_addr_start + y_odd_inc) / S
= (2755 – 8 + 1)/1
2748 rows
V Vertical Blanking ((frame_length_lines – N) * (A + Q)) + Q – (2 * P)
= (2891 – 2748)*7358 + 1862 – 12
1054044 Pixel Clocks
= 6.59 ms
T Frame Valid Time (N * (A + Q)) – Q + (2 * P)
= 2748 * 7358 – 1862 + 12
20217934 Pixel Clocks
= 126.36 ms
F Total Frame Time line_length_pck * frame_length_lines * PIXCLK_PERIOD
= 2891 * 37358
21271978 Pixel Clocks
= 132.95 ms
Table 6. ROW TIMING WITH PARALLEL INTERFACE USING LOW POWER MODE
Parameter
Name Equation Default Timing
PIXCLK_
PERIOD
Pixel Clock Period 1/vt_pix_clk_freq_mhz 1 Pixel Clock
= 12.5 ns
S Skip (Subsampling)
Factor
For x_odd_inc = y_odd_inc = 3, S = 2.
For x_odd_inc = y_odd_inc = 7, S = 4.
otherwise, S = 1
For y_odd_inc = 3, S = 2
For y_odd_inc = 7, S = 4
For y_odd_inc = 15, S = 8
For y_odd_inc = 31, S = 16
For y_odd_inc = 63, S = 32
1
A Active Data Time (x_addr_end – x_addr_start + x_odd_inc) * 0.5 * PIXCLK_PERIOD/S
= (3775−112+1)/2
1832 Pixel Clocks
= 22.9
μs
P Frame Start/end
Blanking
6 * PIXCLK_PERIOD 6 Pixel Clocks
= 75 ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55

MT9J003I12STMUH-GEVB

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Manufacturer:
ON Semiconductor
Description:
Optical Sensor Development Tools 10 MP NAVITAR
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