MT9J003
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53
Figure 54. HiSPi Skew Between Data Signals Within the PHY
tCHSKEW1PHY
Table 34. CHANNEL, PHY AND INTRA-PHY SKEW
(Measurement Conditions: PHY Supply 1.8 V, HiSPi Power Supply 0.8 V, Data Rate 480 MHz, DLL set to 0)
Data Lane Skew in Reference to Clock
tCHSKEW1PHY −150 ps
Table 35. CLOCK DLL STEPS
(Measurement Conditions: PHY Supply 1.8 V, HiSPi Power Supply 0.8 V, Data DLL set to 0)
Clock DLL Step
1 2 3 4 5 Step
Delay @ 480MHz 0.25 0.375 0.5 0.625 0.75 UI
Eye_opening@ 480 MHz 0.85 0.78 0.71 0.71 0.69 UI
Eye_opening@ 360 MHz 0.89 0.83 0.81 0.60 046 UI
1. The Clock DLL Steps 6 and 7 are not recommended by ON Semiconductor for the MT9J003 Rev. 2.
Table 36. DATA DLL STEPS
(Measurement Conditions: PHY Supply 1.8 V, HiSPi Power Supply 0.8 V, Clock DLL set to 0)
Data DLL Step
1 2 4 6 Step
Delay @ 480MHz 0.25 0.375 0.625 0.875 UI
Eye_opening@ 480 MHz 0.79 0.84 0.71 0.61 UI
Eye_opening@ 360 MHz 0.85 0.83 0.82 0.77 UI
1. The Data DLL Steps 3, 5, and 7 are not recommended by ON Semiconductor for the MT9J003 Rev. 2.
