Data Sheet ADV7283
Rev. A | Page 9 of 21
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Ty p e Description
1, 4 DGND Ground
Ground for Digital Supply. The exposed pad and DGND pins must be connected together
to a common ground plane (GND).
2 D
VDDIO
Power Digital Input/Output Power Supply (1.8 V or 3.3 V).
3, 13 D
VDD
Power Digital Power Supply (1.8 V).
5 to 12 P7 to P0 Output Video Pixel Output Ports.
14 XTA L P Output
Output for the External 28.63636 MHz Crystal. Connect this pin to the external
28.63636 MHz crystal, or leave it unconnected if an external 1.8 V, 28.63636 MHz clock
oscillator source is used to clock the ADV7283. The crystal used with the ADV7283 must be
a fundamental crystal.
15 XTA L N Input
Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7283 must
be a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used
to clock the
ADV7283, the output of the oscillator is fed into the XTALN pin.
16 P
VDD
Power
PLL Power Supply (1.8 V).
17,18, 22 to
25
A
IN
1 to A
IN
6 Input Analog Video Input Channels.
19 VREFP Output Internal Voltage Reference Output.
20 VREFN Output Internal Voltage Reference Output.
21 A
VDD
Power Analog Power Supply (1.8 V).
26
INTRQ
Output
Interrupt Request Output. An interrupt occurs when certain signals are detected on the
input video.
27
RESET
Input
System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to
reset the ADV7283 circuitry.
28 ALSB Input
Selector for the I
2
C Write Address. When ALSB is set to Logic 0, the write address is 0x40;
when ALSB is set to Logic 1, the write address is 0x42.
29 SDATA Input/output I
2
C Port Serial Data Input/Output.
30 SCLK Input I
2
C Port Serial Clock Input. The maximum clock rate is 400 kHz.
31
PWRDWN
Input Power-Down Pin. A logic low on this pin places the ADV7283 in power-down mode.
32 LLC Output
Line-Locked Output Clock for Output Pixel Data. The clock output is typically 27 MHz, but it
increases or decreases according to the video line length.
EPAD (EP)
Exposed Pad. The exposed pad and DGND pins must be connected together to a common
ground plane (GND).
12347-057
1
2
3
4
5
6
7
8
DGND
D
VDDIO
D
VDD
DGND
P7
P6
P5
P4
17
18
19
20
21
22
23
24
A
IN
1
A
IN
2
VREFP
VREFN
A
VDD
A
IN
3
A
IN
4
A
IN
5
PIN 1
INDICATOR
ADV7283
LFCSP
TOP VIEW
(Not to Scale)
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
P
VDD
XTALN
XTALP
D
VDD
P0
P1
P2
P3
RESET
ALSB
SDATA
SCLK
PWRDWN
INTRQ
A
IN
6
LLC
NOTES
1. THE EXPOSED PAD AND DGND PINS MUST BE
CONNECTED TOGETHER TO A COMMON GROUND
PLANE (GND).
ADV7283 Data Sheet
Rev. A | Page 10 of 21
THEORY OF OPERATION
The ADV7283 is a versatile one-chip, multiformat video
decoder. The device automatically detects standard analog
baseband video signals compatible with worldwide NTSC, PAL,
and SECAM standards in the form of composite, S-Video, and
component video.
The ADV7283 converts the analog video signals into an 8-bit
YCrCb 4:2:2 video data stream that is compatible with the 8-bit
ITU-R BT.656 interface standard.
The analog video inputs of the ADV7283 accept single-ended,
pseudo differential, and fully differential composite video signals,
as well as S-Video and YPrPb video signals, supporting a wide
range of consumer and automotive video sources.
In differential CVBS mode, the ADV7283, along with an
external resistor divider, provides a common-mode input range
of up to 4 V, enabling the removal of large signal, common-mode
transients present on the video lines.
The advanced I2P function allows the ADV7283 to convert an
interlaced video input into a progressive video output. This
function is performed without the need for external memory.
The ADV7283 uses edge adaptive technology to minimize
video defects on low angle lines.
The AGC and clamp restore circuitry allow an input video
signal peak-to-peak range of 1.0 V p-p at the analog video input
pins of the ADV7283. Alternatively, the AGC and clamp restore
circuitry can be bypassed for manual settings.
The external ac coupling capacitors protect the ADV7283 from
short-to-battery (STB) events on the analog video input pins.
The ADV7283 supports a number of other functions, including
8-bit to 6-bit down dither mode and ACE.
The ADV7283 is programmed via a 2-wire, serial bidirectional
port (I
2
C compatible) and is fabricated in a 1.8 V CMOS
process. The monolithic CMOS construction of the ADV7283
ensures greater functionality with lower power dissipation.
The ADV7283 is provided in a space-saving LFCSP surface-
mount, RoHS-compliant package.
The ADV7283 is available in an automotive grade that is rated
over the40°C to +105°C temperature range, making the device
ideal for automotive applications.
The ADV7283 is also available in a 40°C to +85°C temperature
range, making it ideal for industrial applications.
ANALOG FRONT END
The analog front end (AFE) of the ADV7283 comprises a single
high speed, 10-bit ADC that digitizes the analog video signal
before applying it to the standard definition processor (SDP).
The AFE uses differential channels to the ADC to ensure high
performance in mixed-signal applications and to enable different ial
CVBS inputs to connect directly to the ADV7283.
The AFE also includes an input mux that enables the
application of multiple video signals to the ADV7283. The input
mux allows the application of up to six composite video signals to
the ADV7283.
Current clamps are positioned in front of the ADC to ensure
that the video signal remains within the range of the converter.
A resistor divider network is required before each analog input
channel to ensure that the input signal is kept within the range
of the ADC (see the Input Networks section). Fine clamping of
the video signal is performed downstream by digital fine
clamping within the ADV7283.
Table 9 lists the three ADC clock rates that are determined by
the video input format to be processed. These clock rates ensure
4× oversampling per channel for CVBS, Y/C, and YPrPb modes.
Table 9. ADC Clock Rates
Input Format
ADC Clock Rate
(MHz)
1
Oversampling
Rate per
Channel
CVBS (Composite) 57.27
Y/C (S-Video) 114
YPrPb (Component) 172
1
Based on a 28.63636 MHz crystal between the XTALP and XTALN pins.
The fully differential AFE of the ADV7283 provides inherent
small and large signal noise rejection, improved
electromagnetic interference (EMI) protection, and the ability
to absorb ground bounce. Support is provided for both true
differential and pseudo differential signals.
Data Sheet ADV7283
Rev. A | Page 11 of 21
STANDARD DEFINITION PROCESSOR
The ADV7283 can decode a large selection of baseband video
signals in composite (both single-ended and differential),
S-Video, and component formats. The video processor supports
the following standards:
PAL B, PAL D, PAL G, PAL H, PAL I, PAL M, PAL N,
PAL Nc, PAL 60
NTSC J, NTSC M, NTSC 4.43
SECAM B, SECAM D, SECAM G, SECAM K, SECAM L
Using the SDP, the ADV7283 can automatically detect the video
standard and process it accordingly.
The ADV7283 has a five-line adaptive 2D comb filter that
provides superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to the
video standard and signal quality without user intervention.
Video user controls such as brightness, contrast, saturation, and
hue are also available with the ADV7283.
The ADV7283 implements the patented Adaptive Digital Line
Length Tracking (ADLLT™) algorithm to track varying video line
lengths from sources such as VCRs. ADLLT enables the
ADV7283 to track and decode poor quality video sources such as
VCRs and noisy sources from tuner outputs and camcorders.
The ADV7283 contains a chroma transient improvement (CTI)
processor that sharpens the edge rate of chroma transitions,
resulting in sharper vertical transitions.
The ACE feature of the ADV7283 offers improved visual detail
using an algorithm that automatically varies contrast levels to
enhance picture detail. ACE increases the contrast in dark areas
of an image without saturating the bright areas of the image.
This feature is particularly useful in automotive applications,
where it can be important to discern objects in shaded areas.
Down dithering converts the output of the ADV7283 from an
8-bit to a 6-bit output, enabling ease of design for standard LCD
panels.
The I2P block converts the interlaced video input into a
progressive video output without the need for external memory.
The SDP can process a variety of VBI data services, such as closed
captioning (CCAP), wide screen signaling (WSS), copy generation
management systems (CGMS), and teletext data slicing for
world system teletext (WST).
The ADV7283 is fully Rovi® (Macrovision) compliant; detection
circuitry enables Type I , Ty pe II, and Type III protection levels
to be identified and reported to the user. The decoder is also
fully robust to all Rovi signal inputs.

ADV7283BCPZ-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video ICs 10-bit SD Video Decoder
Lifecycle:
New from this manufacturer.
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