ADV7283 Data Sheet
Rev. A | Page 12 of 21
POWER SUPPLY SEQUENCING
OPTIMAL POWER-UP SEQUENCE
The optimal power-up sequence for the ADV7283 is to first
power up the 3.3 V D
VDDIO
supply, followed by the 1.8 V supplies
(D
VDD
, P
VDD
, and A
VDD
).
When powering up the ADV7283, follow these steps (during
power-up, all supplies must adhere to the specifications listed in
the Absolute Maximum Ratings section):
1. Assert the
PWRDWN
and
RESET
pins (pull the pins low).
2. Power up the D
VDDIO
supply.
3. After D
VDDIO
is fully asserted, power up the 1.8 V supplies.
4. After the 1.8 V supplies are fully asserted, pull
the
PWRDWN
pin high.
5. Wait 5 ms and then pull the
RESET
pin high.
6. After all power supplies and the
PWRDWN
and
RESET
pins
are powered up and stable, wait an additional 5 ms before
initiating I
2
C communication with the ADV7283.
SIMPLIFIED POWER-UP SEQUENCE
Alternatively, the ADV7283 can be powered up by asserting all
supplies and the
PWRDWN
and
RESET
pins simultaneously.
After this operation, perform a software reset, then wait 10 ms
before initiating I
2
C communication with the ADV7283.
While the supplies are being established, ensure that a lower
rated supply does not go above a higher rated supply level.
During power-up, all supplies must adhere to the specifications
listed in the Absolute Maximum Ratings section.
POWER-DOWN SEQUENCE
The ADV7283 supplies can be deasserted simultaneously as
long as D
VDDIO
does not go below a lower rated supply.
D
VDDIO
SUPPLY VOLTAGE
Under normal operating conditions, the ADV7283 operates
with a nominal D
VDDIO
voltage of 3.3 V. The device can also
operate with a nominal D
VDDIO
voltage of 1.8 V. When operating
with a nominal voltage of 1.8 V, apply the power-up sequences
described in the Optimal Power-Up Sequence and Simplified
Power-Up Sequence sections. The only changes are that D
VDDIO
is powered up to 1.8 V instead of 3.3 V, and the
PWRDWN
and
RESET
pins of the ADV7283 are powered up to 1.8 V
instead of 3.3 V.
Note that when the ADV7283 operates with a nominal D
VDDIO
voltage of 1.8 V, t h e n set the drive strength of all digital outputs
to a maximum.
Note that when D
VDDIO
is set to a nominal voltage of 1.8 V, no
pins can be pulled up to 3.3 V. For example, pull the I
2
C pins of
the ADV7283 (SCLK and SDATA) up to 1.8 V instead of
3.3 V.
POWER SUPPLY REQUIREMENTS
Table 10 shows the current rating recommendations for power
supply design. Use these values when designing a power supply
section to ensure that an adequate current is supplied to the
ADV7283.
Table 10. Current Rating Recommendations for Power
Supply Design
Current Rating
I
DVDDIO
20 mA
I
DVDD
110 mA
I
AVDD
100 mA
I
PVDD
20 mA
Figure 5. Optimal Power-Up Sequence
3.3V
1.8V
VOLTAGE
TIME3.3V SUPPLY
POWER-UP
1.8V SUPPLIES
POWER-UP
3.3V SUPPLY
PWRDWN PIN
PWRDWN
PIN
POWER-UP
RESET PIN
POWER-UP
RESET PIN
1.8V SUPPLIES
5ms
RESET
OPERATION
5ms
WAIT
12347-005
Data Sheet ADV7283
Rev. A | Page 13 of 21
INPUT NETWORKS
An input network (external resistor and capacitor circuit) is
required on the A
IN
x input pins of the ADV7283. The
components of the input network depend on the video format
selected for the analog input.
SINGLE-ENDED INPUT NETWORK
Figure 6 shows the input network to use on each A
IN
x input pin
of the ADV7283 when any of the following video input formats
are used:
Single-ended CVBS
Y/C (S-Vide o)
YPrPb
Figure 6. Single-Ended Input Network
The 24 Ω and 51 resistors supply the 75 end termination
required for the analog video input. These resistors also create a
resistor divider with a gain of 0.68. The resistor divider attenuates
the amplitude of the input analog video and scales the input to the
ADC range of the ADV7283. This allows an input range of up to
1.47 V p-p. Note that amplifiers within the ADC restore the
amplitude of the input signal so SNR performance is
maintained.
The 100 nF ac coupling capacitor removes the dc bias of the analog
input video before it is fed into the A
IN
x pins of the ADV7283.
The clamping circuitry within the ADV7283 restores the dc bias
of the input signal to the optimal level before it is fed into the
ADC of the ADV7283.
DIFFERENTIAL INPUT NETWORK
Figure 7 shows the input network to use when differential
CVBS video is input on the A
IN
x input pins of the ADV7283.
Figure 7. Differential Input Network
Fully differential video transmission involves transmitting two
complementary CVBS signals. Pseudo differential video
transmission involves transmitting a CVBS signal and a source
ground signal.
Differential video transmission has several key advantages over
single-ended transmission, including
Inherent small signal and large signal noise rejection
Improved EMI performance
An ability to absorb ground bounce
Resistor R1 provides the RF end termination for the differential
CVBS input lines. For a pseudo differential CVBS input, a value
of 75 Ω is recommended for R1. For a fully differential CVBS
input, a value of 150 Ω is recommended for R1.
The 1.3 kΩ and 430 Ω resistors create a resistor divider with a
gain of 0.25. The resistor divider attenuates the amplitude of the
input analog video, but increases the input common-mode range
of the ADV7283 to 4 V p-p. Note that amplifiers within the
ADC restore the amplitude of the input signal so that SNR
performance is maintained.
The 100 nF ac coupling capacitors remove the dc bias of the
analog input video before it is fed into the A
IN
x pins of the
ADV7283. The clamping circuitry within the ADV7283 restores
the dc bias of the input signal to the optimal level before it is fed
into the ADC of the ADV7283.
The combination of the 1.3 kΩ and 430 resistors and the
100 nF ac coupling capacitors limits the current flow into the
ADV7283 during STB events (see the Short-to-Battery
Protection section).
To achieve optimal performance, the 1.3 kΩ and 430 resistors
must be closely matched; that is, all 1.3 kΩ and 430 resistors
must have the same resistance tolerance, and this tolerance must
be as low as possible.
SHORT-TO-BATTERY PROTECTION
In differential mode, the ADV7283 is protected against STB
events by the external 100 nF ac coupling capacitors (see
Figure 7). The external input network resistors are sized to be
large enough to reduce the current flow during an STB event,
but small enough to avoid affecting the operation of the
ADV7283.
The power rating of the input network resistors must be chosen
withstand the high voltages of STB events. Similarly, ensure that
the breakdown voltage of the ac coupling capacitors is robust
enough to handle STB events.
The R1 resistor is protected because no current or limited current
flows through it during an STB event.
51Ω
A
IN
3
INPUT
CONNECTOR
VIDEO INPUT
FROM SOURCE
24Ω
100nF
EXT
ESD
12347-006
A
IN
1
A
IN
2
POSITIVE
INPUT
CONNECTOR
NEGATIVE
INPUT
CONNECTOR
VIDEO INPUT
FROM SOURCE
EXT
ESD
R1
1.3kΩ
100nF
1.3kΩ
100nF
430Ω
430Ω
12347-007
ADV7283 Data Sheet
Rev. A | Page 14 of 21
APPLICATIONS INFORMATION
INPUT CONFIGURATION
The input format of the ADV7283 is specified using the
INSEL[4:0] bits (see Table 11). These bits also configure the SDP
core to process CVBS, differential CVBS, Y/C (S-Vide o), or
component (YPrPb) format. The INSEL[4:0] bits are located in
the user sub map of the register space at Address 0x00[4:0]. For
more information about the registers, see the Register Maps
section.
The INSEL[4:0] bits specify predefined analog input routing
schemes, eliminating the need for manual mux programming
and allowing the user to route the various video signal types to
the decoder. For example, if the CVBS input is selected, the
remaining channels are powered down.
Table 11. Input Format Specified by the INSEL[4:0] Bits
INSEL[4:0] Bit Value
Video Format
Analog Inputs
00000 CVBS CVBS input on A
IN
1
00001 CVBS CVBS input on A
IN
2
00010 CVBS CVBS input on A
IN
3
00011 CVBS CVBS input on A
IN
4
00100 Reserved Reserved
00101 Reserved Reserved
00110 CVBS CVBS input on A
IN
5
00111 CVBS CVBS input on A
IN
6
01000 Y/C (S-Video) Y input on A
IN
1
C input on A
IN
2
01001 Y/C (S-Video) Y input on A
IN
3
C input on A
IN
4
01010 Reserved Reserved
01011 Y/C (S-Video)
Y input on A
IN
5
C input on A
IN
6
01100 YPrPb Y input on A
IN
1
Pb input on A
IN
2
Pr input on A
IN
3
01101 Reserved Reserved
01110 Differential CVBS Positive input on A
IN
1
Negative input on A
IN
2
01111 Differential CVBS Positive input on A
IN
3
Negative input on A
IN
4
10000 Reserved Reserved
10001 Differential CVBS Positive input on A
IN
5
Negative input on A
IN
6
10010 to 11111 Reserved Reserved

ADV7283BCPZ-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video ICs 10-bit SD Video Decoder
Lifecycle:
New from this manufacturer.
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