ADV7283 Data Sheet
Rev. A | Page 18 of 21
Table 13. I
2
C Register Map and Sub Map Addresses
ALSB Pin
R/
W
Bit
Slave Address
SUB_USR_EN Bits
(Address 0x0E[6:5])
Register Map or Sub Map
0 0 (write) 0x40 00 User sub map
0 1 (read) 0x41 00 User sub map
0 0 (write) 0x40 01 Interrupt/VDP sub map
0 1 (read) 0x41 01 Interrupt/VDP sub map
0 0 (write) 0x40 10 User Sub Map 2
0 1 (read) 0x41 10 User Sub Map 2
1 0 (write) 0x42 00 User sub map
1 1 (read) 0x43 00 User sub map
1 0 (write) 0x42 01 Interrupt/VDP sub map
1 1 (read) 0x43 01 Interrupt/VDP sub map
1 0 (write) 0x42 10 User Sub Map 2
1 1 (read) 0x43 10 User Sub Map 2
X
1
0 (write) 0x84 XX
1
VPP map
X
1
1 (read) 0x85 XX
1
VPP map
1
X and XX m ean don’t care.
PCB LAYOUT RECOMMENDATIONS
The ADV7283 is a high precision, high speed, mixed-signal
device. To achieve maximum performance from the device, it is
important to use a well designed PCB. This section provides
guidelines for designing a PCB for use with the ADV7283.
Analog Interface Inputs
When routing the analog interface inputs on the PCB, keep
track lengths to a minimum. Use 75 Ω trace impedances when
possible; trace impedances other than 75 Ω increase the chance
of reflections.
Power Supply Decoupling
It is recommended that each power supply pin be decoupled
with 100 nF and 10 nF capacitors. The basic principle is to place
a decoupling capacitor within approximately 0.5 cm of each
power pin. Avoid placing the decoupling capacitors on the
opposite side of the PCB from the ADV7283 because doing so
introduces inductive vias in the path.
Place the decoupling capacitors between the power plane and
the power pin. Current must flow from the power plane to the
capacitor and then to the power pin. Do not apply the power
connection between the capacitor and the power pin. The best
approach is to place a via close to or beneath the decoupling
capacitor pads down to the power plane (see Figure 12).
Figure 12. Recommended Power Supply Decoupling
It is especially important to maintain low noise and good
stability for the P
VDD
pin. Pay careful attention to regulation,
filtering, and decoupling. It is highly desirable to provide
separate regulated supplies for each circuit group (A
VDD
, D
VDD
,
D
VDDIO
, and P
VDD
).
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This disparity can
result in a measurable change in the voltage supplied to the analog
supply regulator, which can, in turn, produce changes in the
regulated analog supply voltage. To mitigate this problem,
regulate the analog supply, or at least the P
VDD
supply, from a
different, cleaner power source, for example, from a 12 V supply.
Using a single ground plane for the entire board is recommended.
Using multiple ground planes can be detrimental because each
separate ground plane is smaller, and can result in long ground
loops. Therefore, using a single ground plane can improve noise
performance.
VREFN and VREFP Pins
Place the circuit associated with the VREFN and VREFP pins as
close as possible to the ADV7283 and on the same side of the
PCB as the device.
Digital Outputs
The ADV7283 digital outputs are
INTRQ
, LLC, and P0 to P7.
Minimize the trace length that the digital outputs must drive.
Longer traces have higher capacitance, requiring more current
and, in turn, causing more internal digital noise. Shorter traces
reduce the possibility of reflections.
Adding a 30 Ω to 50 Ω series resistor can suppress reflections,
reduce EMI, and reduce current spikes inside the ADV7283. If
series resistors are used, place them as close as possible to the
SUPPLY
GROUND
10nF
100nF
VIA TO SUPPLY
VIA TO GND
12347-013
NOTES
1. GND REFERS
TO THE COMMON GROUND PLANE
OF THE PCB.
