MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
______________________________________________________________________________________ 13
Detailed Description
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
logic-level translators provide the level shifting neces-
sary to allow data transfer in a multivoltage system.
Externally applied voltages, V
CC
and V
L
, set the logic
levels on either side of the device. Logic signals pre-
sent on the V
L
side of the device appear as a higher
voltage logic signal on the V
CC
side of the device, and
vice-versa. The MAX13101E/MAX13102E/MAX13103E/
MAX13108E are bidirectional level translators allowing
data translation in either direction (V
L
V
CC
) on
any single data line. The MAX13101E/MAX13102E/
MAX13103E/MAX13108E accept V
L
from +1.2V to V
CC
.
All devices have a V
CC
range from +1.65V to +5.5V,
making them ideal for data transfer between low-volt-
age ASICs/PLDs and higher voltage systems.
The MAX13101E/MAX13102E/MAX13103E feature an
output enable mode that reduces V
CC
supply current to
less than 1µA, and V
L
supply current to less than 2µA
when in shutdown. The MAX13108E features a multi-
plexing input that selects one byte between the two,
thus allowing multiplexing of the signals. The
MAX13101E/MAX13102E/MAX13103E/MAX13108E
have ±15kV ESD protection on the I/O V
CC
side for
greater protection in applications that route signals
externally. The MAX13101E/MAX13102E/MAX13103E/
MAX13108E operate at a guaranteed data rate of
20Mbps. The maximum data rate depends heavily
on the load capacitance (see the
Typical Operating
Characteristics
) and the output impedance of the
external driver.
Power-Supply Sequencing
For proper operation, ensure that +1.65V V
CC
+5.5V,
+1.2V V
L
+5.5V, and V
L
V
CC
. During power-up
sequencing, V
L
V
CC
does not damage the device.
When V
CC
is disconnected and V
L
is powering up, up to
10mA of current can be sourced to each load on the V
L
side, yet the device does not latch up. To guarantee that
no excess leakage current flows and that the device
does not interfere with the I/O on the V
L
side, V
CC
should
be connected to GND with a max 50Ω resistor when the
V
CC
supply is not present (Figure 5).
Input Driver Requirements
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
architecture is based on a one-shot accelerator output
stage (Figure 6). Accelerator output stages are always
in tri-state except when there is a transition on any of
the translators on the input side, either I/O V
L
_ or
I/O V
CC
_. Then a short pulse is generated, during
which the accelerator output stages become active and
charge/discharge the capacitances at the I/Os. Due to
the bidirectional nature, both input stages become
active during the one-shot pulse. This can lead to some
current feeding into the external source that is driving
the translator. However, this behavior helps to speed
up the transition on the driven side.
For proper full-speed operation, the output current of a
device that drives the inputs of the MAX13101E/
MAX13102E/MAX13103E/MAX13108E should meet the
following requirement:
i > 10
8
x V x (C + 10pF)
where, i is the driver output current, V is the logic-supply
voltage (i.e., V
L
or V
CC
) and C is the parasitic capaci-
tance of the signal line.
Enable Output Mode (EN)
The MAX13101E/MAX13102E/MAX13103E feature an
enable input (EN) that, when driven low, places the
device into shutdown mode. During shutdown, the
MAX13101E I/O V
CC
_ ports are pulled down to ground
with internal 6kΩ resistors and the I/O V
L
_ ports enter
tri-state. MAX13102E I/O V
CC
_ lines enter tri-state and
the I/OV
L
_ lines are pulled down to ground with internal
6kΩ resistors. All I/O V
CC
_ and I/O V
L
_ lines on the
MAX13103E enter tri-state while the device is in shut-
down mode. During shutdown, the V
CC
supply current
reduces to less than 1µA, and the V
L
supply current
reduces to less than 2µA. To guarantee minimum shut-
down supply current, all I/O V
L
_ need to be driven to
GND or V
L
, or pulled to GND or V
L
through 100kΩ
resistors. All I/O V
CC
_ need to be driven to GND or
V
CC,
or pulled to GND or V
CC
through 100kΩ resistors.
Drive EN to logic-high (V
L
or V
CC
) for normal operation.
I/O V
CC
16 I/O V
L
16
I/O V
L
1
I/O V
CC
1
V
CC
V
L
+1.2V TO +5.5V
GND
V
CC
SUPPLY
V
BATT
DISABLE
R
DSON
< 50Ω
MAX13101E
MAX13102E
MAX13103E
MAX13108E
Figure 5. Recommended Circuit for Powering Down V
CC
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
14 ______________________________________________________________________________________
Multiplexing Input (MULT)
The MAX13108E features a multiplexing input (MULT)
that enables 8 of the 16 channels and places the
remaining 8 into tri-state. Figure 7 depicts a typical mul-
tiplexing configuration using the MAX13108E. Drive
MULT high to enable I/O V
CC
1 through I/O V
CC
8 and
I/O V
L
1 through I/O V
L
8. Driving MULT high sets
I/O V
CC
9 through I/O V
CC
16 and I/O V
L
9 through I/O
V
L
16 into tri-state. Drive MULT low to enable I/O V
CC
9
through I/O V
CC
16 and I/O V
L
9 through I/O V
L
16.
Driving MULT low sets I/O V
CC
1 through I/O V
CC
8 and
I/O V
L
1 through I/O V
L
8 into tri-state.
±15kV ESD Protection
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
The I/O V
CC
_ lines have extra protection against static
discharge. Maxim’s engineers have developed state-of-
the-art structures to protect these pins against ESD of
±15kV without damage. The ESD structures withstand
high ESD in all states: normal operation, tri-state output
mode, and powered down. After an ESD event, Maxim’s
E versions keep working without latchup, whereas com-
peting products can latch and must be powered down
to remove the latchup condition.
ESD protection can be tested in various ways. The
I/O V
CC
_ lines of the MAX13101E/ MAX13102E/
MAX13103E/MAX13108E are characterized for protec-
tion to ±15kV using the Human Body Model.
RISE-TIME
ACCELERATOR
FALL-TIME
ACCELERATOR
I/O V
CC_
I/O V
L_
V
CC
V
L
RISE-TIME
ACCELERATOR
FALL-TIME
ACCELERATOR
MAX13101E
MAX13102E
MAX13103E
MAX13108E
Figure 6. Simplified Diagram (1 I/O Line)
PORT A
PORT B
I/O V
L
9
I/O V
L
10
I/O V
L
11
I/O V
L
12
I/O V
L
13
I/O V
L
14
I/O V
L
15
I/O V
L
16
I/O V
L
3
I/O V
L
4
I/O V
L
5
I/O V
L
6
I/O V
L
7
I/O V
L
8
I/O V
L
1
I/O V
L
2
I/O V
CC
1
MULT
I/O V
CC
2
I/O V
CC
3
I/O V
CC
4
I/O V
CC
5
I/O V
CC
6
I/O V
CC
7
I/O V
CC
8
I/O V
CC
9
I/O V
CC
10
I/O V
CC
11
I/O V
CC
12
I/O V
CC
13
I/O V
CC
14
I/O V
CC
15
I/O V
CC
16
MAX13108E
Figure 7. MAX13108E Multiplexing Configuration
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
______________________________________________________________________________________ 15
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
Human Body Model
Figure 8a shows the Human Body Model and Figure 8b
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the test device
through a 1.5kΩ resistor.
Machine Model
The Machine Model for ESD tests all pins using a
200pF storage capacitor and zero discharge resis-
tance. Its objective is to emulate the stress caused by
contact that occurs with handling and assembly during
manufacturing. All pins require this protection during
manufacturing, not just inputs and outputs. Therefore,
after PC board assembly, the Machine Model is less
relevant to I/O ports.
Applications Information
Power-Supply Decoupling
To reduce ripple and the chance of transmitting incor-
rect data, bypass V
L
and V
CC
to ground with 0.1µF
capacitors. To ensure full ±15kV ESD protection,
bypass V
CC
to ground with a 1µF ceramic capacitor.
Place all capacitors as close to the power-supply inputs
as possible.
Capacitive Loading
Capacitive loading on the I/O lines impacts the rise time
(and fall time) of the MAX13101E/MAX13102E/
MAX13103E/MAX13108E when driving the signal lines.
The actual rise time is a function of the parasitic capaci-
tance, the supply voltage, and the drive impedance of
the MAX13101E/MAX13102E/MAX13103E/MAX13108E.
For proper operation, the signal must reach the V
OH
as
required before the rise-time accelerators turn off.
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
R
C
1MΩ R
D
1500Ω
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
C
S
100pF
Figure 8a. Human Body ESD Test Model
100%
90%
36.8%
t
RL
t
DL
TIME
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
10%
0
0
AMPERES
I
P
I
r
Figure 8b. Human Body Model Current Waveform

MAX13101EETL+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Translation - Voltage Levels 16-Ch 20Mbps 5.5V Logic Level Tr
Lifecycle:
New from this manufacturer.
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