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MAX13101EETL+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
16 ______________________________________________________________________________________
Ordering Information/Selector Guide (continued)
PART PIN-PACKAGE
DATA
RATE (Mbps)
I/O V
L
STATE
DURING SHUTDOWN
I/O V
CC
STATE
DURING SHUTDOWN
MULTIPLEXER
FEATURE
MAX13102EEWX+
36 WLP**
3.06mm x 3.06mm
20 6kΩ to GND High impedance No
MAX13102EETL+
40 TQFN-EP***
5mm x 5mm x 0.8mm
20 6kΩ to GND High impedance No
MAX13103EEWX+
36 WLP**
3.06mm x 3.06mm
20 High impedance High impedance No
MAX13103EETL+
40 TQFN-EP***
5mm x 5mm x 0.8mm
20 High impedance High impedance No
MAX13108EEWX+
36 WLP**
3.06mm x 3.06mm
20 High impedance High impedance Yes
MAX13108EETL+
40 TQFN-EP***
5mm x 5mm x 0.8mm
20 High impedance High impedance Yes
Pin Configurations (continued)
MA131018E
TQFN
+
TOP VIEW OF BOTTOM LEADS
56
4
3
I/O V
L
14
I/O V
L
16
V
L
V
CC
I/O V
CC
16
I/O V
L
13
I/O V
L
3
I/O V
L
1
V
L
I/O V
L
4
V
CC
I/O V
CC
1
11
12
I/O V
L
7
14
15
16
17
I/O V
L
8
I/O V
L
9
I/O V
CC
7
I/O V
CC
8
I/O V
CC
9
I/O V
CC
10
I/O V
L
15
I/O V
L
2
13
7
I/O V
L
10
I/O V
CC
11
8
* EXPOSED PAD CONNECTED TO GROUND
I/O V
L
11
I/O V
L
12
MULT
I/O V
CC
12
GND
9 10
I/O V
L
6
2
I/O V
CC
6
I/O V
L
5
1
I/O V
CC
5
GND
26 25
27
28 24 23 22 212930
I/O V
CC
15
I/O V
CC
14
I/O V
CC
13
I/O V
CC
2
I/O V
CC
3
I/O V
CC
4
18
19
20
40
39
37
36
35
34
38
33
32
31
GND
*EP
Note:
All devices are specified over the -40°C to +85°C operating temperature range.
+
Denotes a lead-free/RoHS-compliant package.
**
WLP bumps are in a 6 x 6 array.
***
EP = Exposed pad.
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
______________________________________________________________________________________ 17
Pin Configurations (continued)
123456
E
D
F
WLP
(BOTTOM VIEW)
WLP
(BOTTOM VIEW)
I/O V
CC
3 I/O V
CC
6 I/O V
CC
9 I/O V
CC
12 I/O V
CC
15
I/O V
CC
1 I/O V
CC
4 I/O V
CC
7 I/O V
CC
10 I/O V
CC
13 I/O V
CC
16
I/O V
CC
2 I/O V
CC
5 I/O V
CC
8 I/O V
CC
11 I/O V
CC
14 GND
I/O V
L
2 I/O V
L
5 I/O V
L
8 I/O V
L
11 I/O V
L
14 EN
I/O V
L
1 I/O V
L
4 I/O V
L
7 I/O V
L
10 I/O V
L
13 I/O V
L
16
V
L
I/O V
L
3 I/O V
L
6 I/O V
L
9 I/O V
L
12 I/O V
L
15
B
A
C
MAX13101E/MAX13102E/MAX13103E
123456
E
D
F
V
CC
V
CC
I/O V
CC
3 I/O V
CC
6 I/O V
CC
9 I/O V
CC
12 I/O V
CC
15
I/O V
CC
1 I/O V
CC
4 I/O V
CC
7 I/O V
CC
10 I/O V
CC
13 I/O V
CC
16
I/O V
CC
2 I/O V
CC
5 I/O V
CC
8 I/O V
CC
11 I/O V
CC
14 GND
I/O V
L
2 I/O V
L
5 I/O V
L
8 I/O V
L
11 I/O V
L
14 MULT
I/O V
L
1 I/O V
L
4 I/O V
L
7 I/O V
L
10 I/O V
L
13 I/O V
L
16
V
L
I/O V
L
3 I/O V
L
6 I/O V
L
9 I/O V
L
12 I/O V
L
15
B
A
C
MAX13108E
++
Chip Information
PROCESS: BiCMOS
Typical Operating Circuit
MAX13101E
MAX13102E
MAX13103E
MAX13108E
+1.8V
+3.3V
+1.8V
SYSTEM
CONTROLLER
+3.3V
SYSTEM
DATA
( ) ARE FOR MAX13108E
DATA
GND
V
L
V
CC
I/O V
CC_
I/O V
L_
EN/(MULT)
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
36 WLP W363A3-1
21-0024
40 TQFN-EP T4055-1
21-0140
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
2 8/06 Release of the MAX13101EETL+ —
3 6/08 Changed UCSP to WLP packaging
1, 2, 9, 10, 11, 16,
17, 18, 19
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

MAX13101EETL+T

Mfr. #:
Buy MAX13101EETL+T
Manufacturer:
Maxim Integrated
Description:
Translation - Voltage Levels 16-Ch 20Mbps 5.5V Logic Level Tr
Lifecycle:
New from this manufacturer.
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