REV. F
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AD7712
LC
2
MOS
Signal Conditioning ADC
FUNCTIONAL BLOCK DIAGRAM
CLOCK
GENERATION
SERIAL INTERFACE
OUTPUT
REGISTER
CHARGE-BALANCING A/D
CONVERTER
AUTO-ZEROED
MODULATOR
DIGITAL
FILTER
AD7712
AGND
DGND
MODE SDATA SCLK
A0
MCLK
OUT
MCLK
IN
AIN1(–)
REF
IN (–)
REF
IN (+)
SYNC
4.5A
A = 1 – 128
DRDY
TFSRFS
REF OUT
V
BIAS
VOLTAGE
ATTENUATION
AIN2
TP
STANDBY
CONTROL
REGISTER
V
SS
2.5V REFERENCE
DV
DD
AV
DD
AV
DD
M
U
X
AIN1(+)
PGA
FEATURES
Charge Balancing ADC
24 Bits No Missing Codes
0.0015% Nonlinearity
High Level and Low Level Analog Input Channels
Programmable Gain for Both Inputs
Gains from 1 to 128
Differential Input for Low Level Channel
Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
Bidirectional Microcontroller Serial Interface
Internal/External Reference Option
Single- or Dual-Supply Operation
Low Power (25 mW typ) with Power-Down Mode
(100 W typ)
APPLICATIONS
Process Control
Smart Transmitters
Portable Industrial Instruments
GENERAL DESCRIPTION
The AD7712 is a complete analog front end for low frequency
measurement applications. The device has two analog input
channels and accepts either low level signals directly from a trans-
ducer or high level (±4 V
REF
) signals, and outputs a serial
digital word. It employs a sigma-delta conversion technique to
realize up to 24 bits of no missing codes performance. The low
level input signal is applied to a proprietary programmable gain
front end based around an analog modulator. The high level
analog input is attenuated before being applied to the same
modulator. The modulator output is processed by an on-chip
digital filter. The first notch of this digital filter can be programmed
via the on-chip control register, allowing adjustment of the filter
cutoff and settling time.
Normally, one of the channels will be used as the main channel
with the second channel used as an auxiliary input to periodi-
cally measure a second voltage. The part can be operated from a
single supply (by tying the V
SS
pin to AGND), provided that the
input signals on the low level analog input are more positive
than –30 mV. By taking the V
SS
pin negative, the part can con-
vert signals down to –V
REF
on this low level input. This low level
input, as well as the reference input, features differential input
capability.
The AD7712 is ideal for use in smart, microcontroller based
systems. Input channel selection, gain settings, and signal polar-
ity can be configured in software using the bidirectional serial
port. The AD7712 also contains self-calibration, system calibra-
tion, and background calibration options, and allows the user to
read and to write the on-chip calibration registers.
CMOS construction ensures low power dissipation, and a hard-
ware programmable power-down mode reduces the standby power
consumption to only 100 µW typical. The part is available in a
24-lead, 0.3 inch wide, plastic and hermetic dual-in-line pack-
age (DIP), as well as a 24-lead small outline (SOIC) package.
PRODUCT HIGHLIGHTS
1. The low level analog input channel allows the AD7712 to
accept input signals directly from a strain gage or transducer,
removing a considerable amount of signal conditioning. To
maximize the flexibility of the part, the high level analog
input accepts signals of ±4 V
REF
/GAIN.
2. The AD7712 is ideal for microcontroller or DSP processor
applications with an on-chip control register that allows
control over filter cutoff, input gain, channel selection, signal
polarity, and calibration modes.
3. The AD7712 allows the user to read and to write the on-chip
calibration registers. This means that the microcontroller has
much greater control over the calibration procedure.
4. No missing codes ensures true, usable, 23-bit dynamic range
coupled with excellent ±0.0015% accuracy. The effects of
temperature drift are eliminated by on-chip self-calibration,
which removes zero-scale and full-scale errors.
AD7712* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
EVALUATION KITS
AD7712 Evaluation Board
DOCUMENTATION
Application Notes
AN-202: An IC Amplifier User’s Guide to Decoupling,
Grounding, and Making Things Go Right for a Change
AN-283: Sigma-Delta ADCs and DACs
AN-311: How to Reliably Protect CMOS Circuits Against
Power Supply Overvoltaging
AN-388: Using Sigma-Delta Converters-Part 1
AN-389: Using Sigma-Delta Converters-Part 2
AN-397: Electrically Induced Damage to Standard Linear
Integrated Circuits:
AN-406: Using the AD771X Family of 24-Bit Sigma-Delta
A/D Converters
AN-553: Adjusting the Calibration Coefficients on the
AD771X Family of ADCs
AN-607: Selecting a Low Bandwidth (<15 kSPS) Sigma-
Delta ADC
AN-615: Peak-to-Peak Resolution Versus Effective
Resolution
Data Sheet
AD7712: LC
2
MOS Signal Conditioning ADC Data Sheet
TOOLS AND SIMULATIONS
Sigma-Delta ADC Tutorial
REFERENCE MATERIALS
Technical Articles
Delta-Sigma Rocks RF, As ADC Designers Jump On Jitter
MS-2210: Designing Power Supplies for High Speed ADC
Part 1: Circuit Suggestions Using Features and
Functionality of New Sigma-Delta ADCs
Part 2: Circuit Suggestions Using Features and
Functionality of New Sigma-Delta ADCs
DESIGN RESOURCES
AD7712 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
View all AD7712 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
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REV. F–2–
AD7712–SPECIFICATIONS
Parameter A, S Versions
1
Unit Conditions/Comments
STATIC PERFORMANCE
No Missing Codes 24 Bits min Guaranteed by Design. For Filter Notches 60 Hz
22 Bits min For Filter Notch = 100 Hz
18 Bits min For Filter Notch = 250 Hz
15 Bits min For Filter Notch = 500 Hz
12 Bits min For Filter Notch = 1 kHz
Output Noise See Tables I and II Depends on Filter Cutoffs and Selected Gain
Integral Nonlinearity @ 25°C ±0.0015 % FSR max Filter Notches 60 Hz
T
MIN
to T
MAX
±0.003 % FSR max Typically ± 0.0003%
Positive Full-Scale Error
2, 3, 4
Excluding Reference
Full-Scale Drift
5
1 µV/°C typ Excluding Reference. For Gains of 1, 2
0.3 µV/°C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
Unipolar Offset Error
2, 4
Unipolar Offset Drift
5
0.5 µV/°C typ For Gains of 1, 2
0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128
Bipolar Zero Error
2, 4
Bipolar Zero Drift
5
0.5 µV/°C typ For Gains of 1, 2
0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128
Gain Drift 2 ppm/°C typ
Bipolar Negative Full-Scale Error
2
@ 25°C ±0.003 % FSR max Excluding Reference
T
MIN
to T
MAX
±0.006 % FSR max Typically ± 0.0006%
Bipolar Negative Full-Scale Drift
5
1 µV/°C typ Excluding Reference. For Gains of 1, 2
0.3 µV/°C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
ANALOG INPUTS/REFERENCE INPUTS
Normal-Mode 50 Hz Rejection
6
100 dB min For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 f
NOTCH
Normal-Mode 60 Hz Rejection
6
100 dB min For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 f
NOTCH
AIN1/REF IN
DC Input Leakage Current
@ 25°C
6
10 pA max
T
MIN
to T
MAX
1 nA max
Sampling Capacitance
6
20 pF max
Common-Mode Rejection (CMR) 100 dB min At dc and AV
DD
= 5 V
90 dB min At dc and AV
DD
= 10 V
Common-Mode 50 Hz Rejection
6
150 dB min For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 f
NOTCH
Common-Mode 60 Hz Rejection
6
150 dB min For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 f
NOTCH
Common-Mode Voltage Range
7
V
SS
to AV
DD
V min to V max
Analog Inputs
8
Input Sampling Rate, f
S
See Table III
AIN1 Input Voltage Range
9
For Normal Operation. Depends on Gain Selected
0 V to V
REF
10
V max Unipolar Input Range (B/U Bit of Control Register = 1)
±V
REF
V max Bipolar Input Range (B/U Bit of Control Register = 0)
AIN2 Input Voltage Range
9
For Normal Operation. Depends on Gain Selected
0 V to 4 V
REF
10
V max Unipolar Input Range (B/U Bit of Control Register = 1)
±4 V
REF
V max Bipolar Input Range (B/U Bit of Control Register = 0)
AIN2 DC Input Impedance 30 k
AIN2 Gain Error
11
±0.05 % typ Additional Error Contributed by Resistor Attenuator
AIN2 Gain Drift 1 ppm/°C typ Additional Drift Contributed by Resistor Attenuator
AIN2 Offset Error
11
10 mV max Additional Error Contributed by Resistor Attenuator
AIN2 Offset Drift 20 µV/°C typ
Reference Inputs
REF IN(+) – REF IN(–) Voltage
12
2.5 to 5 V min to V max For Specified Performance. Part Is Functional with
Lower V
REF
Voltages
Input Sampling Rate, f
S
f
CLK IN
/256
NOTES
1
Temperature range is as follows: A Version, –40°C to +85°C; S Version –55°C to +125°C. See also Note 18.
2
Applies after calibration at the temperature of interest.
3
Positive full-scale error applies to both unipolar and bipolar input ranges.
4
These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 µV typical after self-calibration
or background calibration.
5
Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
6
These numbers are guaranteed by design and/or characterization.
7
This common-mode voltage range is allowed, provided that the input voltage on AIN1(+) and AIN1(–) does not exceed AV
DD
+ 30 mV and V
SS
– 30 mV.
8
The AIN1 analog input presents a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended
source resistance depends on the selected gain (see Tables IV and V).
9
The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1(–) input. The input voltage range on the AIN2
input is with respect to AGND. The absolute voltage on the AIN1 input should not go more positive than AV
DD
+ 30 mV or more negative than V
SS
– 30 mV.
10
V
REF
= REF IN(+) – REF IN(–).
11
This error can be removed using the system calibration capabilities of the AD7712. This error is not removed by the AD7712’s self-calibration features. The offset
drift on the AIN2 input is 4 times the value given in the Static Performance section.
12
The reference input voltage range may be restricted by the input voltage range requirement on the V
BIAS
input.
(AV
DD
= +5 V 5%; DV
DD
= +5 V 5%; V
SS
= 0 V or –5 V 5%; REF IN(+) = +2.5 V;
REF IN(–) = AGND; MCLK IN = 10 MHz unless otherwise stated. All specifications T
MIN
to T
MAX
, unless otherwise noted.)

AD7712ANZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS 24-Bit w/ 2 Analog Inpt Ch
Lifecycle:
New from this manufacturer.
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