REV. F
AD7712
–9–
Control Register (24 Bits)
A write to the device with the A0 input low writes data to the control register. A read to the device with the A0 input low accesses the
contents of the control register. The control register is 24 bits wide and when writing to the register 24 bits of data must be written
otherwise the data will not be loaded to the control register. In other words, it is not possible to write just the first 12 bits of data into
the control register. If more than 24 clock pulses are provided before TFS returns high, then all clock pulses after the 24th clock
pulse are ignored. Similarly, a read operation from the control register should access 24 bits of data.
MSB
MD2 MD1 MD0 G2 G1 G0 CH PD WL X BO B/U
FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0
X = Don’t Care. LSB
Operating Mode
MD2 MD1 MD0 Operating Mode
000Normal Mode. This is the normal mode of operation of the device whereby a read to the device accesses
data from the data register. This is the default condition of these bits after the internal power-on reset.
001Activate Self-Calibration. This activates self-calibration on the channel selected by CH. This is a one-step
calibration sequence, and when complete, the part returns to normal mode (with MD2, MD1, MD0 of
the control registers returning to 0, 0, 0). The DRDY output indicates when this self-calibration is complete.
For this calibration type, the zero-scale calibration is done internally on shorted (zeroed) inputs, and the
full-scale calibration is done on V
REF
.
010Activate System Calibration. This activates system calibration on the channel selected by CH. This is a
two-step calibration sequence, with the zero-scale calibration done first on the selected input channel and
DRDY indicating when this zero-scale calibration is complete. The part returns to normal mode at the
end of this first step in the two-step sequence.
011Activate System Calibration. This is the second step of the system calibration sequence with full-scale
calibration being performed on the selected input channel. Once again, DRDY indicates when the full-
scale calibration is complete. When this calibration is complete, the part returns to normal mode.
100Activate System Offset Calibration. This activates system offset calibration on the channel selected by
CH. This is a one-step calibration sequence and, when complete, the part returns to normal mode with
DRDY indicating when this system offset calibration is complete. For this calibration type, the zero-scale
calibration is done on the selected input channel, and the full-scale calibration is done internally on V
REF
.
101Activate Background Calibration. This activates background calibration on the channel selected by CH. If
the background calibration mode is on, then the AD7712 provides continuous self-calibration of the
reference and shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence,
extending the conversion time and reducing the word rate by a factor of 6. Its major advantage is that
the user does not have to worry about recalibrating the device when there is a change in the ambient
temperature. In this mode, the shorted (zeroed) inputs and V
REF
, as well as the analog input voltage, are
continuously monitored, and the calibration registers of the device are automatically updated.
110Read/Write Zero-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents
of the zero-scale calibration coefficients of the channel selected by CH. A write to the device with A0 high
writes data to the zero-scale calibration coefficients of the channel selected by CH. The word length for
reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control
register. Therefore, when writing to the calibration register, 24 bits of data must be written; otherwise the
new data will not be transferred to the calibration register.
111Read/Write Full-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents of
the full-scale calibration coefficients of the channel selected by CH. A write to the device with A0 high
writes data to the full-scale calibration coefficients of the channel selected by CH. The word length for
reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control
register. Therefore, when writing to the calibration register, 24 bits of data must be written; otherwise the
new data will not be transferred to the calibration register.
REV. F–10–
AD7712
PGA Gain
G2 Gl G0 Gain
00 01 (Default Condition after the Internal Power-On Reset)
00 1 2
01 0 4
01 1 8
10 0 16
10 1 32
11 0 64
11 1 128
Channel Selection
CH Channel
0AIN1Low Level Input (Default Condition after the Internal Power-On Reset)
1 AIN2 High Level Input
Power-Down
PD
0Normal Operation (Default Condition after the Internal Power-On Reset)
1 Power-Down
Word Length
WL Output Word Length
0 16-Bit (Default Condition after Internal Power-On Reset)
1 24-Bit
Burnout Current
BO
0Off (Default Condition after Internal Power-On Reset)
1On
Bipolar/Unipolar Selection (Both Inputs)
B/U
0 Bipolar (Default Condition after Internal Power-On Reset)
1 Unipolar
Filter Selection (FS11–FS0)
The on-chip digital filter provides a sinc
3
(or (sinx/x)
3
) filter
response. The 12 bits of data programmed into these bits deter-
mine the filter cutoff frequency, the position of the first notch of
the filter, and the data rate for the part. In association with the
gain selection, it also determines the output noise (and therefore
the effective resolution) of the device.
The first notch of the filter occurs at a frequency determined by
the relationship filter first notch frequency = (f
CLK IN
/512)/code
where code is the decimal equivalent of the code in bits FS0 to
FS11 and is in the range 19 to 2,000. With the nominal f
CLK IN
of
10 MHz, this results in a first notch frequency range from 9.76 Hz
to 1.028 kHz. To ensure correct operation of the AD7712, the
value of the code loaded to these bits must be within this range.
Failure to do this will result in unspecified operation of the device.
Changing the filter notch frequency, as well as the selected gain,
impacts resolution. Tables I and II and Figure 2 show the effect
of the filter notch frequency and gain on the effective resolution
of the AD7712. The output data rate (or effective conversion
time) for the device is equal to the frequency selected for the
first notch of the filter. For example, if the first notch of the filter
is selected at 50 Hz, then a new word is available at a 50 Hz rate
or every 20 ms. If the first notch is at 1 kHz, a new word is avail-
able every 1 ms.
The settling time of the filter to a full-scale step input change is
worst case 4 1/(output data rate). This settling time is to
100% of the final value. For example, with the first filter notch
at 50 Hz, the settling time of the filter to a full-scale step input
change is 80 ms max. If the first notch is at 1 kHz, the settling
time of the filter to a full-scale input step is 4 ms max. This
settling time can be reduced to 3 l/(output data rate) by syn-
chronizing the step input change to a reset of the digital filter. In
other words, if the step input takes place with SYNC low, the
settling time will be 3 l/(output data rate). If a change of
channels takes place, the settling time is 3 l/(output data rate)
regardless of the SYNC input.
The –3 dB frequency is determined by the programmed first
notch frequency according to the relationship filter –3 dB
frequency = 0.262 first notch frequency.
REV. F
AD7712
–11–
Tables I and II show the output rms noise for some typical
notch and –3 dB frequencies. The numbers given are for the
bipolar input ranges with a V
REF
of 2.5 V. These numbers are
typical and are generated with an analog input voltage of 0 V.
The output noise from the part comes from two sources. First,
there is the electrical noise in the semiconductor devices used in
the implementation of the modulator (device noise). Second,
when the analog input signal is converted into the digital do-
main, quantization noise is added. The device noise is at a low
level and is largely independent of frequency. The quantization
noise starts at an even lower level but rises rapidly with increasing
frequency to become the dominant noise source. Consequently,
lower filter notch settings (below 60 Hz approximately) tend to
be device noise dominated while higher notch settings are domi-
nated by quantization noise. Changing the filter notch and cutoff
frequency in the quantization noise dominated region results in a
more dramatic improvement in noise performance than it does
in the device noise dominated region as shown in Table I.
Furthermore, quantization noise is added after the PGA, so
effective resolution is independent of gain for the higher filter
Table I. Output Noise vs. Gain and First Notch Frequency
First Notch of
Filter and O/P –3 dB Gain of Gain of Gain of Gain of Gain of Gain of Gain of Gain of
Data Rate
1
Frequency 1248163264128
10 Hz
2
2.62 Hz 1.0 0.78 0.48 0.33 0.25 0.25 0.25 0.25
25 Hz
2
6.55 Hz 1.8 1.1 0.63 0.5 0.44 0.41 0.38 0.38
30 Hz
2
7.86 Hz 2.5 1.31 0.84 0.57 0.46 0.43 0.4 0.4
50 Hz
2
13.1 Hz 4.33 2.06 1.2 0.64 0.54 0.46 0.46 0.46
60 Hz
2
15.72 Hz 5.28 2.36 1.33 0.87 0.63 0.62 0.6 0.56
100 Hz
3
26.2 Hz 13 6.4 3.7 1.8 1.1 0.9 0.65 0.65
250 Hz
3
65.5 Hz 130 75 25 12 7.5 4 2.7 1.7
500 Hz
3
131 Hz 0.6 10
3
0.26 10
3
140 70 35 25 15 8
1 kHz
3
262 Hz 3.1 10
3
1.6 10
3
0.7 10
3
0.29 10
3
180 120 70 40
NOTES
1
The default condition (after the internal power-on reset) for the first notch of filter is 60 Hz.
2
For these filter notch frequencies, the output rms noise is primarily dominated by device noise, and, as a result, is independent of the value of the reference voltage.
Therefore, increasing the reference voltage will give an increase in the effective resolution of the device (i.e., the ratio of the rms noise to the input full scale is
increased since the output rms noise remains constant as the input full scale increases).
3
For these filter notch frequencies, the output rms noise is dominated by quantization noise, and, as a result, is proportional to the value of the reference voltage.
Table II. Effective Resolution vs. Gain and First Notch Frequency
First Notch of
Filter and O/P –3 dB Gain of Gain of Gain of Gain of Gain of Gain of Gain of Gain of
Data Rate Frequency 1248163264128
10 Hz 2.62 Hz 22.5 21.5 21.5 21 20.5 19.5 18.5 17.5
25 Hz 6.55 Hz 21.5 21 21 20 19.5 18.5 17.5 16.5
30 Hz 7.86 Hz 21 21 20.5 20 19.5 18.5 17.5 16.5
50 Hz 13.1 Hz 20 20 20 20 19 18.5 17.5 16.5
60 Hz 15.72 Hz 20 20 20 19.5 19 18 17 16
100 Hz 26.2 Hz 18.5 18.5 18.5 18.5 18 17.5 17 16
250 Hz 65.5 Hz 15 15.5 15.5 15.5 15.5 15.5 15 14.5
500 Hz 131 Hz 13 13 13 13 13 12.5 12.5 12.5
1 kHz 262 Hz 10.5 10.5 11 11 11 10.5 10 10
*Effective resolution is defined as the magnitude of the output rms noise with respect to the input full scale (i.e., 2 V
REF
/GAIN). The above table applies for
a V
REF
of 2.5 V and resolution numbers are rounded to the nearest 0.5 LSB.
Typical Output RMS Noise (V)
Effective Resolution* (Bits)
notch frequencies. Meanwhile, device noise is added in the PGA
and, therefore, effective resolution suffers a little at high gains
for lower notch frequencies.
At the lower filter notch settings (below 60 Hz), the no missing
codes performance of the device is at the 24-bit level. At the
higher settings, more codes will be missed until at the 1 kHz
notch setting; no missing codes performance is guaranteed only
to the 12-bit level. However, since the effective resolution of the
part is 10.5 bits for this filter notch setting, this no missing codes
performance should be more than adequate for all applications.
The effective resolution of the device is defined as the ratio of
the output rms noise to the input full scale. This does not
remain constant with increasing gain or with increasing band-
width. Table II is the same as Table I except that the output is
expressed in terms of effective resolution (the magnitude of the
rms noise with respect to 2 V
REF
/GAIN, i.e., the input full
scale). It is possible to do post filtering on the device to improve
the output data rate for a given –3 dB frequency and to further
reduce the output noise (see the Digital Filtering section).

AD7712ANZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS 24-Bit w/ 2 Analog Inpt Ch
Lifecycle:
New from this manufacturer.
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