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AD7712ANZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
REV. F–6–
AD7712
Limit at T
MIN
, T
MAX
Parameter (A, S Versions) Unit Conditions/Comments
External Clocking Mode
f
SCLK
f
CLK IN
/5 MHz max Serial Clock Input Frequency
t
20
0 ns min DRDY to RFS Setup Time
t
21
0 ns min DRDY to RFS Hold Time
t
22
2 ⫻ t
CLK IN
ns min A0 to RFS Setup Time
t
23
0 ns min A0 to RFS Hold Time
t
24
7
4 ⫻ t
CLK IN
ns max Data Access Time (RFS Low to Data Valid)
t
25
7
10 ns min SCLK Falling Edge to Data Valid Delay
2 ⫻ t
CLK IN
+ 20 ns max
t
26
2 ⫻ t
CLK IN
ns min SCLK High Pulse Width
t
27
2 ⫻ t
CLK IN
ns min SCLK Low Pulse Width
t
28
t
CLK IN
+ 10 ns max SCLK Falling Edge to DRDY High
t
29
8
10 ns min SCLK to Data Valid Hold Time
t
CLK IN
+ 10 ns max
t
30
10 ns min RFS/TFS to SCLK Falling Edge Hold Time
t
31
8
5 ⫻ t
CLK IN
/2 + 50 ns max RFS to Data Valid Hold Time
t
32
0 ns min A0 to TFS Setup Time
t
33
0 ns min A0 to TFS Hold Time
t
34
4 ⫻ t
CLK IN
ns min SCLK Falling Edge to TFS Hold Time
t
35
2 ⫻ t
CLK IN
– SCLK High ns min Data Valid to SCLK Setup Time
t
36
30 ns min Data Valid to SCLK Hold Time
NOTES
8
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are
the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
Specifications subject to change without notice.
TO OUTPUT
PIN
2.1V
1.6mA
200␮A
100pF
Figure 1. Load Circuit for Access Time and
Bus Relinquish Time
PIN CONFIGURATION
DIP and SOIC
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7712
AV
DD
V
SS
TP
STANDBY
AIN1(–)
MCLK IN
MCLK OUT
A0
AIN1(+)
MODE
SCLK
SYNC
V
BIAS
REF IN(–)
REF IN(+)
REF OUT
AIN2
DGND
DV
DD
SDATA
DRDY
AGND
TFS
RFS
TIMING CHARACTERISTICS
(continued)
REV. F
AD7712
–7–
PIN FUNCTION DESCRIPTION
Pin Mnemonic Function
1 SCLK Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the
device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK becomes
active when RFS or TFS goes low, and it goes high impedance when either RFS or TFS returns high or when
the device has completed transmission of an output word. When MODE is low, the device is in its external
clocking mode, and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all
data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the
information being transmitted to the AD7712 in smaller batches of data.
2 MCLK IN Master Clock Signal for the Device. This can be provided in the form of a crystal or external clock. A crystal can
be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a
CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 10 MHz.
3 MCLK OUT When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT.
4A0Address Input. With this input low, reading and writing to the device is to the control register. With this input
high, access is to either the data register or the calibration registers.
5 SYNC Logic Input. Allows for synchronization of the digital filters when using a number of AD7712s. It resets
the nodes of the digital filter.
6 MODE Logic Input. When this pin is high, the device is in its self-clocking mode. With this pin low, the device is in its
external clocking mode.
7 AIN1(+) Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input
is connected to an output current source that can be used to check that an external transducer has burned out
or gone open circuit. This output current source can be turned on/off via the control register.
8 AIN1(–) Analog Input Channel 1. Negative input of the programmable gain differential analog input.
9 STANDBY Logic Input. Taking this pin low shuts down the internal analog and digital circuitry, reducing power
consumption to less than 50 µW.
10 TP Test Pin. Used when testing the device. Do not connect anything to this pin.
11 V
SS
Analog Negative Supply, 0 V to –5 V. Tied to AGND for single-supply operation. The input voltage on AIN1
should not go > 30 mV negative w.r.t. V
SS
for correct operation of the device.
12 AV
DD
Analog Positive Supply Voltage, 5 V to 10 V.
13 V
BIAS
Input Bias Voltage. This input voltage should be set such that V
BIAS
+ 0.85 ⫻ V
REF
< AV
DD
and V
BIAS
– 0.85
⫻ V
REF
> V
SS
where V
REF
is REF IN(+) – REF IN(–). Ideally, this should be tied halfway between AV
DD
and V
SS
. Thus, with AV
DD
= +5 V and V
SS
= 0 V, it can be tied to REF OUT; with AV
DD
= +5 V and V
SS
=
–5 V, it can be tied to AGND, while with AV
DD
= +10 V, it can be tied to +5 V.
14 REF IN(–) Reference Input. The REF IN(–) can lie anywhere between AV
DD
and V
SS
provided REF IN(+) is greater
than REF IN(–).
15 REF IN(+) Reference Input. The reference input is differential providing that REF IN(+) is greater than REF IN(–).
REF IN(+) can lie anywhere between AV
DD
and V
SS
.
16 REF OUT Reference Output. The internal 2.5 V reference is provided at this pin. This is a single-ended output
that is referred to AGND.
17 AIN2 Analog Input Channel 2. High level analog input that accepts an analog input voltage range of ± 4 ⫻
V
REF
/GAIN. At the nominal V
REF
of +2.5 V and a gain of 1, the AIN2 input voltage range is ±10 V.
18 AGND Ground Reference Point for Analog Circuitry.
19 TFS Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial
data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active
after TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data-word
is written to the part.
20 RFS Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the
self-clocking mode, both the SCLK and SDATA lines become active after RFS goes low. In the external
clocking mode, the SDATA line becomes active after RFS goes low.
REV. F–8–
AD7712
Pin Mnemonic Function
21 DRDY Logic Output. A falling edge indicates that a new output word is available for transmission. The DRDY pin
will return high upon completion of transmission of a full output word. DRDY is also used to indicate
when the AD7712 has completed its on-chip calibration sequence.
22 SDATA Serial Data. Input/output with serial data being written to either the control register or the calibration
registers and serial data being accessed from the control register, calibration registers, or the data register.
During an output data read operation, serial data becomes active after RFS goes low (provided DRDY is
low). During a write operation, valid serial data is expected on the rising edges of SCLK when TFS is low.
The output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs.
23 DV
DD
Digital Supply Voltage, 5 V. DV
DD
should not exceed AV
DD
by more than 0.3 V in normal operation.
24 DGND Ground Reference Point for Digital Circuitry.
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end-
points of the transfer function are zero-scale (not to be confused
with bipolar zero), a point 0.5 LSB below the first code transi-
tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB
above the last code transition (111 ...110 to 111 . . . 111). The
error is expressed as a percentage of full scale.
Positive Full-Scale Error
Positive full-scale error is the deviation of the last code transi-
tion (111 . . . 110 to 111 ...111) from the ideal input full-scale
voltage. For AIN1(+), the ideal full-scale input voltage is
(AIN1(–) + V
REF
/GAIN – 3/2 LSBs); for AIN2, the ideal full-
scale voltage is +4 ⫻ V
REF
/GAIN – 3/2 LSBs. Positive full-scale
error applies to both unipolar and bipolar analog input ranges.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal voltage. For AIN1(+), the ideal input voltage is
(AIN1(–) + 0.5 LSB); for AIN2, the ideal input is 0.5 LSB
when operating in the unipolar mode.
Bipolar Zero Error
This is the deviation of the midscale transition (0111 . . . 111
to 1000 ...000) from the ideal input voltage. For AIN1(+), the
ideal input voltage is (AIN1(–) – 0.5 LSB); for AIN2, the ideal
input is –0.5 LSB when operating in the bipolar mode.
Bipolar Negative Full-Scale Error
This is the deviation of the first code transition from the ideal
input voltage. For AIN1(+), the ideal input voltage is (AIN1(–)
– V
REF
/GAIN + 0.5 LSB); for AIN2, the ideal input voltage is
(–4 ⫻ V
REF
/GAIN + 0.5 LSB) when operating in the bipolar
mode.
Positive Full-Scale Overrange
Positive full-scale overrange is the amount of overhead available
to handle input voltages on AIN1(+) input greater than
(AIN1(–) + V
REF
/GAIN) or on the AIN2 of greater than +4 ⫻
V
REF
/GAIN (for example, noise peaks or excess voltages due to
system gain errors in system calibration routines) without intro-
ducing errors due to overloading the analog modulator or to
overflowing the digital filter.
Negative Full-Scale Overrange
This is the amount of overhead available to handle voltages on
AIN1(+) below (AIN1(–) – V
REF
/GAIN) or on AIN2 below
–4 ⫻ V
REF
/GAIN without overloading the analog modulator or
overflowing the digital filter. Note that the analog input will
accept negative voltage peaks on AIN1(+) even in the unipolar
mode provided that AIN1(+) is greater than AIN1(–) and greater
than V
SS
– 30 mV.
Offset Calibration Range
In the system calibration modes, the AD7712 calibrates its
offset with respect to the analog input. The offset calibration
range specification defines the range of voltages that the AD7712
can accept and still accurately calibrate offset.
Full-Scale Calibration Range
This is the range of voltages that the AD7712 can accept in the
system calibration mode and still correctly calibrate full scale.
Input Span
In system calibration schemes, two voltages applied in sequence
to the AD7712’s analog input define the analog input range.
The input span specification defines the minimum and maxi-
mum input voltages from zero to full scale that the AD7712 can
accept and still accurately calibrate gain.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

AD7712ANZ

Mfr. #:
Buy AD7712ANZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS 24-Bit w/ 2 Analog Inpt Ch
Lifecycle:
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