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STMPE801MTR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
I2C module STMPE801
10/26
Figure 4. I
2
C timing
5.2 I
2
C features
The features that are supported by the I
2
C interface are as below:
● I
2
C slave device
● Operates at 1.8V
● Compliant to Philips I
2
C specification version 2.1
● Supports standard (uo to 100Kbps) and fast (up to 400Kbps) modes
Table 7. I
2
C address
Symbol Parameter Min Typ Max Unit
f
SCL
SCL clock frequency 0 400 kHz
t
LOW
Clock low period 1.3 µs
t
HIGH
Clock high period 600 ns
t
F
SDA and SCL fall time 300 ns
t
HD:STA
START condition hold time
(After this period the first clock is generated)
600 ns
t
SU:STA
START condition setup time
(Only relevant for a repeated start period)
600 ns
t
SU:DAT
Data setup time 100 ns
t
HD:DAT
Data hold time 0 µs
t
SU:STO
STOP condition setup time 600 ns
t
BUF
Time the bust must be free before a new
trasmission can start
1.3 µs
STMPE801 I2C module
11/26
5.3 Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and will not respond to any transaction unless one is
encountered.
5.4 Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state.
A Stop condition terminates communication between the slave device and bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
next I
2
C transaction. A Stop condition at the end of a write command stops the write
operation to registers.
5.5 Acknowledge bit
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it would to not acknowledge the receipt of the data.
5.6 Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
I2C module STMPE801
12/26
5.7 Operation modes
Figure 5. Read and write modes (random and sequential)
Table 8. Operation modes
Mode Bytes Programming Sequence
Read ≥1
START, Device Address, R/W
= 0, Register Address to be read
RESTART, Device Address, R/W
= 1, Data Read, STOP
If no STOP is issued, the Data Read can be continuously preformed. If
the register address falls within the range that allows address auto-
increment, then register address auto-increments internally after every
byte of data being read. For register address that falls within a non-
incremental address range, the address will be kept static throughout the
entire read operations. Refer to the Memory Map table for the address
ranges that are auto and non-increment.
Write ≥1
START, Device Address, R/W
= 0, Register Address to be written, Data
Write, STOP
If no STOP is issued, the Data Write can be continuously performed. If
the register address falls within the range that allows address auto-
increment, then register address auto-increments internally after every
byte of data being written in. For register address that falls within a non-
incremental address range, the address will be kept static throughout the
entire write operations. Refer to the Memory Map table for the address
ranges that are auto and non-increment.
One Byte
Re ad
Start
RnW=0
Ack
Ack
reStart
RnW=1
Ack
NoAck
Stop
More than
One Byte
Re ad
Start
RnW=0
Ack
Ack
reStart
RnW=1
Ack
Ack
Ack
NoAck
Stop
One Byte
Write
Start
RnW=0
Ack
Ack
Ack
Stop
M
ore
th
an
One Byte
Write
Start
RnW=0
Ack
Ack
Ack
Ack
Ack
Stop
Master
Slave
Data to
Write + 1
Data to
Write + 2
Dev
Addr
Reg
Addr
Data to
Write
Data
Read + 1
Data
Read + 2
Dev
Addr
Reg
Addr
Data to
be
Written
Dev
Addr
Reg
Addr
Dev
Addr
Data
Read
Dev
Addr
Reg
Addr
Dev
Addr
Data
Read
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STMPE801MTR

Mfr. #:
Buy STMPE801MTR
Manufacturer:
STMicroelectronics
Description:
Interface - I/O Expanders 8B port expander Xpander logic
Lifecycle:
New from this manufacturer.
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