Interrupt, power supply & reset STMPE801
16/26
8 Interrupt, power supply & reset
STMPE801 could be configured to generate an interrupt when there is a logic transition of
any of the GPIO configured as input.
8.1 Interrupt enable GPIO mask register (IEGPIOR)
IEGPIOR register is used to enable the interruption from a particular GPIO interrupt source
to the host. The IEG[7:0] bits are the interrupt enable mask bits correspond to the GPIO[7:0]
pins.
IEGPIOR
Bit765 432 1 0
IEG7 IEG6 IEG5 IEG4 IEG3 IEG2 IEG1 IEG0
R/WRWRWRW RWRWRW RW RW
Reset
Value
000 000 0 0
Table 13. Register
Bits Name Description
7:0 IEG[x]
Interrupt Enable GPIO Mask (where x = 7 to 0)
Writing a ‘1’ to the IE[x] bit will enable the interruption to the host.
STMPE801 Interrupt, power supply & reset
17/26
8.2 Interrupt status GPIO register (ISGPIOR)
ISGPIOR register monitors the status of the interruption from a particular GPIO pin interrupt
source to the host. Regardless whether the IEGPIOR bits are enabled or not, the ISGPIOR
bits are still updated. The ISG[9:0] bits are the interrupt status bits correspond to the
GPIO[7:0] pins.
8.3 GPIO controller
A total of 8 GPIOs are available in the STMPE801 port expander IC. The GPIO controller
contains the registers that allow the host system to configure each of the pins as input or
output. Unused GPIOs should be configured as outputs to minimize the power consumption.
A group of registers are used to control the exact function of each of the 8 GPIO. The
registers and their respective address is listed in the following table.
ISGPIOR
Bit 7 6 5 4 3 2 1 0
ISG7 ISG6 ISG5 ISG4 ISG3 ISG2 ISG1 ISG0
R/W RW RW RW RW RW RW RW RW
Reset
Value
00 0 0 0 0 0 0
Table 14. Register
Bits Name Description
7:0 ISG[x]
Interrupt Status GPIO (where x = 7 to 0)
Read:
Interrupt Status of the GPIO[x]. Reading the register will clear any bits that
has been set to ‘1’
Write:
Writing to this register has no effects
Table 15. Register
Address Register Name Description
Auto-Increment
(during sequential R/W)
0x10 GPMR GPIO monitor pin state register Yes
0x11 GPSR GPIO set pin state register Yes
0x12 GPDR GPIO set pin direction register Yes
Interrupt, power supply & reset STMPE801
18/26
All GPIO registers are named as GPxx, where
Xxx represents the functional group
The function of each bit is shown in the following table:
On power-up reset, all GPIO are set as input.
8.4 Power supply
STMPE801 GPIO operates from a separate supply pin (V
IO
). This dedicated supply pin
provides a level-shifting feature to the STMPE801.
GPIO will remain valid until V
IO
is removed.
The host system may choose to turn off V
CC
supply while keeping V
IO
supplied.
However it is not allowed to turn off supply to V
IO
, while keeping the Vcc supplied.
8.5 Reset
STMPE801 is equipped with an internal POR circuit that holds the device in reset state, until
the V
IO
supply input is valid. The internal POR is tied to the Vio supply pin.
The reset pin allows the host to reset the STMPE801 directly. Minimum pulse width of reset
signal is 100µs.
During the period when reset pin is asserted, all GPIO default to inputs.
Bit 76543210
GPxx IO-7 IO-6 IO-5 IO-4 IO-3 IO-2 IO-1 IO-0
Table 16. Pin function
Register Name Function
GPIO Monitor Pin State Reading this bit yields the current state of the bit. Writing has no effect.
GPIO Set Pin State Writing ‘1’ to this bit causes the corresponding GPIO to go to ‘1’ state.
Writing ‘0’ to this bit causes the corresponding GPIO to go to ‘0’ state.
GPIO Set Pin Direction ‘0’ sets the corresponding GPIO to input state, and ‘1’ sets it to output
state. All bits are ‘0’ on reset.

STMPE801MTR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Interface - I/O Expanders 8B port expander Xpander logic
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet