STMPE801MTR Datasheet STMPE801MTR, STMPE801QTR | P13-P15

STMPE801 I2C module

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5.8 Read operation

A write is first performed to load the register address into the Address Counter but without

sending a Stop condition. Then, the bus master sends a reStart condition and repeats the

Device Address with the R/W

bit set to 1. The slave device acknowledges and outputs the

content of the addressed byte. If no more data is to be read, the bus master must not

acknowledge the byte and terminates the transfer with a Stop condition.

If the bus master acknowledges the data byte, then it can continue to perform the data

reading. To terminate the stream of data byte, the bus master must not acknowledge the

last output byte and follow by a Stop condition. If the address of the register written into the

Address Counter falls within the range of addresses that has the auto-increment function,

the data being read will be coming from consecutive addresses, with the internal Address

Counter automatically increments after each byte output. After the last memory address,

the Address Counter 'rolls-over' and the device continue to output data from the memory

address of 0x00. Similarly, for the address of register that falls within non-increment range

of addresses, the output data byte comes from the same address (which is the address

pointed by the Address Counter).

5.9 Acknowledgement in read operation

For the above read command, the slave device waits, after each byte read, for an

acknowledgement during the ninth bit time. If the bus master does not drive the SDA to low

state, then the slave device terminates and switches back to its idle mode, waiting for the

next command.

5.10 Write operations

A write is first performed to load the register address into the Address Counter without

sending a Stop condition. After the bus master receives an acknowledgement from the

slave device, it may start to send a data byte to the register (pointed by the Address

Counter). The slave device again acknowledges and the bus master terminates the transfer

with a Stop condition.

If the bus master would like to continue to write more data, it can just continue write

operation without issuing the Stop condition. Whether the Address Counter auto-

increments or not after each data byte write, depends on the address of the register written

into the Address Counter. After the bus master writes the last data byte and the slave

device acknowledges the receipt of the last data, the bus master may terminates the write

operation by sending a Stop condition. When the Address Counter reaches the last

memory address, it 'rolls-over' on the next data byte write.

Turning I2C block OFF and ON STMPE801

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5.11 General call

A general call address is a transaction with the slave address of 0x00 and R/W = 0. When a

general call address is made, the device responds to this transaction with an

acknowledgement and behaves as a slave-receiver mode. The meaning of a general call

address is defined in the second byte sent by the master-transmitter.

Note: All other second byte value will be ignored.

6 Turning I

C block OFF and ON

STMPE801 operates entirely on the I

C clock. When there are no activity on the I

C bus,

current consumption of the device is extremely low. However, when there are activity on the

C bus, current consumption increases, even if the I

C traffic is not directed to the assigned

address.

Host system may choose to shut-down the I

C block in the STMPE801, if no access to the

registers are required. This feature allows the current consumption to drop to the minimum.

Host system turns OFF the I

C block by writing ‘1’ into the I

C_SHDN bit. The I

C block will

shut down on the next valid clock edge of the I

C clock signal. In this state, the device

CANNOT be accessed by I

C, as the I

C has shut down completely.

To turn ON the I

C block, system host must reset the STMPE801 in order to re-activate the

C block. This could be done by hardware assertion of the RESET pin.

Table 9. General call

R/W Second Byte Value Definition

0 0x06 2-byte transaction in which the second byte tells the slave device

to reset and write (or latch in) the 1-bit programmable part of the

slave address.

0 0x04 2-byte transaction in which the second byte tells the slave device

not to reset and write (or latch in) the 1-bit programmable part of

the slave address.

0 0x00 Not allowed as second byte.

STMPE801 Register map

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7 Register map

7.1 System and identification registers

7.2 System control register

Table 10. Register map

Address Register Name Size (bit) Function

0x00 Chip ID 16 0x0801

0x02 Version ID 8 Revision number

0x04 SystemControl 8 Reset and interrupt control

0x08 IEGPIOR 8 GPIO interrupt enable register

0x09 ISGPIOR 8 GPIO interrupt status register

0x10 GPMR 8 GPIO monitor pin state register

0x11 GPSR 8 GPIO set pin state register

0x12 GPDR 8 GPIO set pin direction register

Table 11. System and identification registers

Chip ID 16 0x0801

Version ID 8 Revision number:

0x01 (Engineering)

0x02 (Final silicon)

Systemcontrol 8

Table 12. System control register

Bit Reset Name Description

7 0 SoftReset Writing ‘1’ to this bit causes a soft reset

6 0 I2C_SHDN

Writing ‘1’ to this bit shuts down the I2C block

on the next valid I2C clock.

5 0

4 0

3 0

2 0 INT_Enable ‘1’ to enable, ‘0’ to disable INT output

1 0

0 0 INTPolarity ‘1’ for active HI, ‘0’ for active LOW

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

STMPE801MTR

Mfr. #:

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Interface - I/O Expanders 8B port expander Xpander logic

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STMPE801MTR

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