STMPE801 Maximum rating
7/26
3 Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
3.1 Absolute maximum rating
3.2 Thermal data
Table 3. Absolute maximum rating
Symbol Parameter Value Unit
V
CC
Supply voltage 4.5 V
V
IO
GPO supply voltage 4.5 V
VESD (HBM) ESD protection on each GPO pin 2 KV
Table 4. Thermal data
Symbol Parameter
Value
Unit
Min Typ Max
T
A
Operating ambient temperature -40 +85 °C
T
STG
Operating storage temperature -65 155 °C/W
Electrical specification STMPE801
8/26
4 Electrical specification
4.1 DC electrical characteristics
Table 5. DC electrical characteristics
Symbol Parameter Test conditions
Value
Unit
Min Typ Max
V
CC
Core supply voltage 1.65 - 3.6 V
V
IO
IO supplì voltage 1.65 - 3.6 V
Ipd Power down current 1 µA
Icc Max
Operating current
(No peripheral activity)
I
2
C running at 400KHz
100% traffic density
0.2 0.5 mA
Icc
Normal
Operating current
(No peripheral activity)
I
2
C running at 400KHz
1% traffic density
10 15 µA
I
CC
Suspend
Operating current
(No peripheral activity)
No I
2
C activity
0.5 1 µA
V
IL
Input voltage low state
V
IO
= 1.8-3.3V
-0.3V
0.30V
IO
V
V
IH
Input voltage high state
V
IO
= 1.8-3.3V 0.70V
IO
V
IO
+0.3V
V
V
OL
Output voltage low state
V
IO
= 1.8-3.3V, I
OL
=8mA
-0.3V
0.25V
IO
V
V
OH
Output voltage high
state
V
IO
=1.8-3.3V, I
OL
=8mA 0.75V
IO
V
IO
+0.3V
V
V
OL
(I
2
C)
Output voltage low state
Vcc=1.8-3.3V, I
OL
=8mA
-0.3V
0.25V
CC
V
V
OH
(I
2
C)
Output voltage high
state
Vcc=1.8-3.3V, I
OL
=8mA
0.75Vc
c
V
CC
+0.3V
V
STMPE801 I2C module
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5 I
2
C module
STMPE801 is interface to the main processor using an I2C bus.
5.1 I
2
C address
Addressing scheme of STMPE801 is designed to allow up to 2 devices to be connected to
the same I
2
C bus.
Figure 3. Addressing scheme
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition anf followed by the slave device address. Accompanying the slave device address,
there is a Read/Write
bit (R/W). The bit is set to 1 for Read and 0 for write operation.
If a match occurs on the slave device address, the corresponding device gives an
acknowledge on the SDA during the 9
th
bit time. If there is no match, it deselects itself from
the bus by not responding to the transaction.
Table 6. Addresses
ADDR0 Address Note
0 0x82
1 0x88

STMPE801MTR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Interface - I/O Expanders 8B port expander Xpander logic
Lifecycle:
New from this manufacturer.
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