MAX1217
1.8V, Dual, 12-Bit, 125Msps ADC for
Broadband Applications
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Detailed Description
Theory of Operation
The MAX1217 uses a fully differential pipelined archi-
tecture that allows for high-speed conversion, opti-
mized accuracy, and linearity while minimizing power
consumption.
Both positive inputs (INAP, INBP) and negative/comple-
mentary analog inputs (INAN, INBN) are centered
around a 0.8V common-mode voltage, and each
accept a ±V
FS
/ 4 differential analog input voltage
swing, providing a 1.475V
P-P
typical differential full-
scale signal swing. Each set of inputs (INAP, INAN and
INBP, INBN) is sampled when the differential sampling
clock signal transitions high. When using the clock-
divide mode, the analog inputs are sampled at every
other high transition of the differential sampling clock.
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital out-
put code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. The result is a 12-bit parallel
digital output word in selectable two’s-complement or
offset binary output formats with LVDS-compatible out-
put levels (Figure 1).
Analog Inputs
The MAX1217 features two sets of fully differential
inputs (INAP, INAN and INBP, INBN) for each input
channel. Differential inputs feature good rejection of
even-order harmonics, which allows for enhanced AC
performance as the signals are progressing through
the analog stages. The MAX1217 analog inputs are
self-biased at a 0.8V common-mode voltage and allow
a 1.475V
P-P
differential input voltage swing (Figure 2).
Both sets of inputs are self-biased through 1kΩ resis-
tors, resulting in a typical 2kΩ differential input resis-
tance. Drive the analog inputs of the MAX1217 in
AC-coupled configuration to achieve best dynamic per-
formance. See the
Transformer-Coupled, Differential
Analog Input Drive
section.
On-Chip Reference Circuit
The MAX1217 features an internal 1.24V bandgap ref-
erence circuit (Figure 3), which, in combination with two
internal reference-scaling amplifiers, determines the
FSR of each channel. Bypass REFA and REFB with a
0.1µF capacitor to AGND. Adjust the voltage of the
bandgap reference for each channel independently by
adding an external resistor (e.g., 100kΩ trim poten-
tiometer) between REFADJA/REFADJB and AGND or
REFADJA/REFADJB and REFA/REFB to compensate
for gain errors or increase the FSR of each channel.
See the
Applications Information
section for a detailed
description of this process.
To disable the internal reference for each channel, con-
nect the reference adjust input (REFADJA, REFADJB)
to AV
CC
. Apply an external, stable reference to the
channel’s reference input/output (REFA, REFB) to set
the converter’s full scale. To enable the internal refer-
ence for a channel, connect the appropriate reference
adjust input (REFADJA, REFADJB) to AGND.
Clock Inputs (CLKP, CLKN)
Drive the clock inputs of the MAX1217 with an LVDS-
compatible clock to achieve the best dynamic perfor-
mance. The clock signal source must be a high-quality,
low phase noise to avoid any degradation in the noise
performance of the ADC. The clock inputs (CLKP,
CLKN) are internally biased to 1.15V to accept a typical
0.5V
P-P
differential signal swing (Figure 4). See the
Differential, AC-Coupled LVPECL-Compatible Clock
Input
section for more circuit details on how to drive
CLKP and CLKN appropriately. Although not recom-
mended, the clock inputs also accept a single-ended
input signal.
The MAX1217 also features an internal clock-manage-
ment circuit (duty-cycle equalizer) to ensure that the
clock signal applied to inputs CLKP and CLKN is
processed to provide a 50% duty-cycle clock signal that
desensitizes the performance of the converter to varia-
tions in the duty cycle of the input clock source. The
clock duty-cycle equalizer cannot be turned off exter-
nally and requires a minimum 40MHz clock frequency to
allow the device to meet data sheet specifications.
If the MAX1217 is not clocked, the digital outputs begin
to change state randomly, resulting in a supply current
increase of up to 40mA.
Clock Outputs (DCON, DCOP)
The MAX1217 features a differential clock output, which
can be used to latch the digital output data with an
external latch or receiver. Additionally, the clock output
can be used to synchronize external devices (e.g.,
FPGAs) to the ADC. DCOP and DCON are differential
outputs with LVDS-compatible voltage levels. There is a
5.2ns (typ) delay between the rising (falling) edge of
CLKP (CLKN) and the rising (falling) edge of DCOP
(DCON). See Figure 5 for timing details.
Divide-by-2 Clock Control
The MAX1217 offers a clock control line (CLKDIV) that
supports the reduction of clock jitter in a system.
Connect CLKDIV to OGND to enable the ADC’s internal
