MAX1217
1.8V, Dual, 12-Bit, 125Msps ADC for
Broadband Applications
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The MAX1217 dynamic performance depends on the
use of a very clean clock source. The phase noise floor
of the clock source has a negative impact on the SNR
performance. Spurious signals on the clock signal
source also affect the ADC’s dynamic range. The pre-
ferred method of clocking the MAX1217 is differentially
with LVDS- or LVPECL-compatible input levels. The fast
data transition rates of these logic families minimize the
clock input circuitry’s transition uncertainty, thus
improving the SNR performance. To accomplish this,
AC-couple a 50Ω reverse-terminated clock signal
source with low phase noise into a fast differential
receiver, such as the MAX9388 (Figure 7). The receiver
produces the necessary LVPECL output levels to drive
the clock inputs of the data converter.
Transformer-Coupled, Differential
Analog Input Drive
The MAX1217 provides the best SFDR and THD perfor-
mance with fully differential input signals. In differential input
mode, even-order harmonics are lower since the inputs to
each channel (INAP/N and INBP/N) are balanced, and
each of the channel’s inputs only requires half the signal
swing compared to a single-ended configuration.
Wideband RF transformers provide an excellent solu-
tion to convert a single-ended signal to a fully differen-
tial signal. Apply a secondary-side termination to a 1:1
transformer (e.g., Mini-Circuit’s ADT1-1WT) by two sep-
arate 24.9Ω resistors. Higher source impedance values
can be used at the expense of a degradation in dynam-
ic performance. Use resistors with tight tolerance
(0.5%) to minimize effects of imbalance, maximizing the
ADC’s dynamic range. This configuration optimizes
THD and SFDR performance of the ADC by reducing
the effects of transformer parasitics. However, the
source impedance combined with the shunt capaci-
tance provided by a PC board and the ADC’s parasitic
capacitance limit the ADC’s full-power input bandwidth.
To further enhance THD and SFDR performance at high
input frequencies (> 100MHz) place a second trans-
former (Figure 8) in series with the single-ended-to-differ-
ential conversion transformer. The second transformer
reduces the increase of even-order harmonics at high
frequencies.
Single-Ended, AC-Coupled Analog Inputs
Although not recommended, the MAX1217 can be used
in single-ended mode (Figure 9). AC-couple the analog
signals to the positive input of each channel (INAP,
INBP) through a 0.1µF capacitor terminated with a 49.9Ω
resistor to AGND. Terminate the negative input of each
channel (INAN, INBN) with a 24.9Ω resistor in series with
a 0.1µF capacitor to AGND. In single-ended mode the
input range is limited to approximately half of the FSR of
the device, and dynamic performance usually degrades.
Grounding, Bypassing, and
Board Layout
The MAX1217 requires board layout design techniques
suitable for high-speed data converters. This ADC
accepts separate analog and output power supplies.
The analog and output power-supply inputs accept
1.71V to 1.89V input voltage ranges. Although both AV
CC
and OV
CC
can be supplied from one source, use sepa-
rate sources to reduce performance degradation caused
Table 1. MAX1217 Digital Output Coding
