SPI modes M25P10-A
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Example: C
p
= 50 pF, that is R*C
p
= 5 µs <=> the application must ensure that the Bus
Master never leaves the SPI bus in the high impedance state for a time period shorter than
s.
Figure 4. SPI modes supported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
M25P10-A Operating features
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4 Operating features
4.1 Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one
byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is
followed by the internal Program cycle (of duration t
PP
).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Page Program (PP)
and Table 16: Instruction times (device grade 6)).
4.2 Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the
entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of
duration t
SE
or t
BE
).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.3 Polling during a Write, Program or Erase cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase
(SE or BE) can be achieved by not waiting for the worst case delay (t
W
, t
PP
, t
SE
, or t
BE
). The
Write In Progress (WIP) bit is provided in the Status Register so that the application program
can monitor its value, polling it to establish when the previous Write cycle, Program cycle or
Erase cycle is complete.
4.4 Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S
) is High, the device is deselected, but could remain in the Active Power
mode until all internal cycles have completed (Program, Erase, Write Status Register). The
device then goes in to the Standby Power mode. The device consumption drops to I
CC1
.
The Deep Power-down mode is entered when the specific instruction (the Deep Power-
down (DP) instruction) is executed. The device consumption drops further to I
CC2
. The
device remains in this mode until another specific instruction (the Release from Deep
Power-down and Read Electronic Signature (RES) instruction) is executed.
While in the Deep Power-down mode, the device ignores all write, program and erase
instructions (see Deep Power-down (DP)). This can be used as an extra software protection
mechanism, when the device is not in active use, to protect the device from inadvertent
write, program or erase instructions.
Operating features M25P10-A
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4.5 Status Register
The Status Register contains a number of status and control bits, as shown in Table 6, that
can be read or set (as appropriate) by specific instructions. For a detailed description of the
Status Register bits, see Section 6.4: Read Status Register (RDSR).
4.6 Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P10-A features the following data protection mechanisms:
Power On Reset and an internal timer (t
PUW
) can provide protection against inadvertent
changes while the power supply is outside the operating specification.
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected mode (SPM).
The Write Protect (W) signal, in co-operation with the Status Register Write Disable
(SRWD) bit, allows the Block Protect (BP1, BP0) bits and Status Register Write Disable
(SRWD) bit to be write-protected. This is the Hardware Protected mode (HPM).
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection, as all write, program and erase instructions are ignored.

M25P10-AVMN6T

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
IC FLASH 1M SPI 50MHZ 8SO
Lifecycle:
New from this manufacturer.
Delivery:
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