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M25P10-AVMN6T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
Instructions M25P10-A
28/51
6.9 Sector Erase (SE)
The Sector Erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S
) Low, followed by the
instruction code, and three address bytes on Serial Data input (D). Any address inside the
sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S
)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 15.
Chip Select (S
) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S
) is driven High, the self-timed Sector Erase cycle (whose duration is t
SE
) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect
(BP1, BP0) bits (see Table 3 and Tabl e 2) is not executed.
Figure 15. Sector Erase (SE) instruction sequence
1. Address bits A23 to A17 are Don’t care.
24-bit address
C
D
AI03751D
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
M25P10-A Instructions
29/51
6.10 Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S
) Low, followed by the
instruction code on Serial Data input (D). Chip Select (S
) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 16.
Chip Select (S
) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S
)
is driven High, the self-timed Bulk Erase cycle (whose duration is t
BE
) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if both Block Protect (BP1, BP0) bits are 0.
The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 16. Bulk Erase (BE) instruction sequence
C
D
AI03752D
S
21 345670
Instruction
Instructions M25P10-A
30/51
6.11 Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as a software
protection mechanism, while the device is not in active use, as in this mode, the device
ignores all write, program and erase instructions.
Driving Chip Select (S
) High deselects the device, and puts the device in the Standby mode
(if there is no internal cycle currently in progress). But this mode is not the Deep Power-
down mode. The Deep Power-down mode can only be entered by executing the Deep
Power-down (DP) instruction, to reduce the standby current (from I
CC1
to I
CC2
, as specified
in Ta bl e 1 4).
To take the device out of Deep Power-down mode, the Release from Deep Power-down and
Read Electronic Signature (RES) instruction must be issued. No other instruction must be
issued while the device is in Deep Power-down mode.
The Release from Deep Power-down, and Read Electronic Signature (RES) instruction and
the Read Identification (RDID) instruction also allow the electronic signature of the device to
be output on Serial Data output (Q).
The Deep Power-down mode automatically stops at power-down, and the device always
powers-up in the Standby mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S
) Low, followed
by the instruction code on Serial Data input (D). Chip Select (S
) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 17.
Chip Select (S
) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
Chip Select (S
) is driven High, it requires a delay of t
DP
before the supply current is reduced
to I
CC2
and the Deep Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 17. Deep Power-down (DP) instruction sequence
C
D
AI03753D
S
21 345670
t
DP
Deep Power-down mode
Standby mode
Instruction
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

M25P10-AVMN6T

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Buy M25P10-AVMN6T
Manufacturer:
STMicroelectronics
Description:
IC FLASH 1M SPI 50MHZ 8SO
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