M25P10-A Instructions
25/51
6.7 Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on Serial Data output (Q), each bit
being shifted out, at a maximum frequency f
C
, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S
) High. Chip Select (S) can be driven High at any time during data output. Any
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence
1. Address bits A23 to A17 are Don’t care.
C
D
AI04006
S
Q
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24-bit address
0
C
D
S
Q
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy byte
MSB
7 6543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
Instructions M25P10-A
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6.8 Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S
) Low, followed by
the instruction code, three address bytes and at least one data byte on Serial Data input (D).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S
)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 14.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 Data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Table 16: Instruction
times (device grade 6)).
Chip Select (S
) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S
) is driven High, the self-timed Page Program cycle (whose
duration is t
PP
) is initiated. While the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP1, BP0) bits (see Table 3 and Tabl e 2) is not executed.
M25P10-A Instructions
27/51
Figure 14. Page Program (PP) instruction sequence
1. Address bits A23 to A17 are Don’t care.
C
D
AI04082B
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-bit address
0
765432 0
1
Data byte 1
39
51
765432 0
1
Data byte 2
765432 0
1
Data byte 3 Data byte 256
2079
2078
2077
2076
2075
2074
2073
765432 0
1
2072
MSB
MSB
MSB MSB MSB

M25P10-AVMN6T

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
IC FLASH 1M SPI 50MHZ 8SO
Lifecycle:
New from this manufacturer.
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