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X45620V20I-2.7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
1
®
FN8250.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X45620
Dual Voltage Monitor with Integrated
System Battery Switch and EEPROM
FEATURES
• Dual voltage monitoring
• Active low reset outputs
• Two standard reset threshold voltages
—Factory programmable threshold
• Lowline Output — zero delayed POR
• Reset signal valid to V
CC
= 1V
• System battery switch-over circuitry
• Selectable watchdog timer
—(0.15s, 0.4s, 0.8s, off)
• 256Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
programmable Block Lock
™
protection
—In circuit programmable ROM mode
• Minimize EEPROM programming time
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 400kHz 2-wire Interface
• 2.7V to 5.5V power supply operation
• Available package — 20-lead TSSOP
• Dual supervisor
• Battery switch and output
DESCRIPTION
The Intersil X45620 combines power-on reset control,
battery switch circuit, watchdog timer, supply voltage
supervision, secondary voltage supervision, block lock
protect and serial EEPROM in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET
active for a period of
time. This allows the power supply and oscillator to
stabilize before the processor can execute code.
A system battery switch circuit compares V
CC
(V1MON)
with V
BATT
input and connects V
OUT
to whichever is
higher. This provides voltage to external SRAM or other
circuits in the event of main power failure. The X45620
can drive 50mA from V
CC
and 250µA from V
BATT
. The
device switches to V
BATT
when V
CC
drops below the
low V
CC
voltage threshold and V
BATT >
V
CC
.
BLOCK DIAGRAM
Watchdog
Timer Reset
Data
Register
Command
Decode, Test
& Control
Logic
SDA
SCL
V
CC
Reset &
Watchdog
Timebase
Power-on,
Generation
V
CC
Monitor
+
-
Reset
Low Voltage
Status
Register
Protect Logic
EEPROM
Watchdog Transition
Detector
WP
512 X 512
Address-Decoder
V
TRIP1
Logic
V2 Monitor
+
-
V
TRIP2
Logic
System
Switch
RESET/MR
LOWLINE
V2FAIL
V2MON
V
BATT
V
OUT
(V1MON)
Battery
Array
Device
Select
Logic
S0
S1
BATT-ON
WDO
V
OUT
V
OUT
(32K X 8 Bit)
Data Sheet July 29, 2005
2
FN8250.0
July 29, 2005
DESCRIPTION (Continued)
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO
signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The device’s low V
CC
detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when V
CC
(V1MON) falls below the mini-
mum V
CC
trip point (V
TRIP1
). RESET is asserted until
V
CC
returns to proper operating level and stabilizes. A
second voltage monitor circuit tracks the unregulated
supply or monitors a second power supply voltage to
provide a power fail warning. Intersil’s unique circuits
allow the threshold for either voltage monitor to be
reprogrammed to meet special needs or to fine-tune
the threshold for applications requiring higher preci-
sion. (Contact factory for custom V
TRIP
options)
PIN CONFIGURATION
Ordering Information
20-Pin TSSOP
S0
NC
S1
1
2
3
4
NC
V
CC
(V1MON)
BATT-ON
V
OUT
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
LOWLINE
V2FAIL
V2MON
RESET
/MR
WDO
V
SS
V
BATT
NC
NC
SCL
SDA
WP
V
CC
Range V
TRIP1
Range V
TRIP2
Range Package
Operating
Temperature Range Part Number
4.75–5.5V 4.5–4.75V 2.55–2.7V 20L TSSOP 0°C–70°C X45620V20
-40°C–85°C X45620V20I
2.7–5.5V 2.55–2.7V 1.7–1.80V 20L TSSOP 0°C–70°C X45620V20-2.7
-40°C–85°C X45620V20I-2.7
PIN DESCRIPTION
Pin Name Function
1
S
0
Device Select Input. This pin has an internal pull down resistor. (>10MΩ typical)
2
S
1
Device Select Input. This pin has an internal pull down resistor. (>10MΩ typical)
3 NC No internal connections
4LOWLINE
Low V
CC
Detect. This open drain output signal goes LOW when V
CC
< V
TRIP1
and immediately
goes HIGH when V
CC
> V
TRIP1
.
5 NC No internal connections
6V2FAIL
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V
TRIP2
and
goes HIGH when V2MON exceeds V
TRIP2
. There is no power-up reset delay circuitry on this pin.
7V2MONV2 Voltage Monitor Input. When the V2MON input is less than the V
TRIP2
voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V
SS
or V
CC
when not used.
X45620
3
FN8250.0
July 29, 2005
8 RESET
/MR
Reset Output/Manual Reset Input. This is an Input/Output pin.
RESET
Output. This is an active LOW, open drain output which goes active whenever V
CC
falls
below the minimum V
CC
sense level. When RESET is active communication to the device is interrupt-
ed. RESET
remains active until V
CC
rises above the minimum V
CC
sense level for t
PURST
. RESET
also goes active on power-up and remains active for t
PURST
after the power supply stabilizes.
MR
Input. This is an active LOW debounced input. When MR is active, the RESET pins are assert-
ed. When MR
is released, the RESET remains asserted for t
PURST
, and then released.
9WDO
Watchdog Output. WDO is an active low, open drain output which goes active whenever the
watchdog timer goes active. WDO
remains active for 150ms, then returns to the inactive state.
10 V
SS
Ground
11 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It is an open
drain output, requires the use of a pull-up resistor.
14 SCL Serial Clock. The SCL input is used to clock all data into and out of the device.
12–13 NC No internal connections
15 V
BATT
Battery Supply Voltage. This input provides a backup supply in the event of a failure of the pri-
mary V
CC
voltage. The V
BATT
voltage typically provides the supply voltage necessary to maintain
the contents of SRAM and also powers the internal logic to “stay awake.” If unused, connect V
BATT
to ground.
16 V
OUT
Output Voltage.
V
OUT
= V
CC
if V
CC
> V
TRIP1
.
IF V
CC
< V
TRIP1
, then,
V
OUT
= V
CC
if V
CC
> V
BATT
+0.03
V
OUT
= V
BATT
if V
CC
< V
BATT
-0.03
Note: There is hysteresis around V
BATT
± 0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability.
17 BATT-ON Battery On. This CMOS output goes HIGH when the V
OUT
switches to V
BATT
and goes LOW
when V
OUT
switches to V
CC
. It is used to drive a external P-channel FET when V
CC
= V
OUT
and
current requirements are greater than 50mA.
The purpose of this output is to drive an external FET to get higher operating currents when the
V
CC
supply is fully functional. In the event of a V
CC
failure, the battery voltage is applied to the
V
OUT
pin and the external transistor is turned off. In this “backup condition,” the battery only needs
to supply enough voltage and current to keep SRAM devices from losing their data-there is no
communication at this time.
18 NC No Connect
19 WP Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits.
This pin has an internal pull down
resistor. (>10MΩ typical)
20 V
CC
(V1MON)
Supply Voltage/V1 Voltage Monitor Input. When the V1MON input is less than the VTRIP1
voltage, RESET
and LOWLINE go ACTIVE.
PIN DESCRIPTION (Continued)
Pin Name Function
X45620
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

X45620V20I-2.7

Mfr. #:
Buy X45620V20I-2.7
Manufacturer:
Renesas / Intersil
Description:
IC VOLT MON DUAL SW EEPR 20TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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