X45620V20I-2.7 Datasheet X45620V20I, X45620V20I-2.7 | P16-P18

FN8250.0

July 29, 2005

Figure 13. Acknowledge Polling Sequence

READ OPERATIONS

Read operations are initiated in the same manner as

write operations with the exception that the R/W

bit of

the Slave Address Byte is set to one. There are three

basic read operations: Current Address Reads, Ran-

dom Reads, and Sequential Reads. Refer to bus tim-

ing on page 21.

Current Address Read

Internally, the device contains an address counter that

maintains the address of the last word read or written

incremented by one. After a read operation from the

last address in the array, the counter will “roll over” to

the first address in the array. After a write operation to

the last address in a given page, the counter will “roll

over” to the first address on the same page.

Upon receipt of the Slave Address Byte with the R/W

bit

set to one, the device issues an acknowledge and then

transmits the eight bits of the Data Byte. The master ter-

minates the read operation when it does not respond

with an acknowledge during the ninth clock and then

issues a stop condition. Refer to Figure 14 for the

address, acknowledge, and data transfer sequence.

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read

operation, the master must either issue a stop condi-

tion during the ninth cycle or hold SDA HIGH during

the ninth clock cycle and then issue a stop condition.

Note: After a power-up sequence, the first read cannot

be a current address read.

Figure 14. Current Address Read Sequence

Random Read

Random read operation allows the master to access

any memory location in the array. Prior to issuing the

Slave Address Byte with the R/W

bit set to one, the

master must first perform a “Dummy” write operation.

The master issues the start condition and the Slave

Address Byte with the R/W

bit low, receives an

acknowledge, then issues the Word Address Byte 1,

receives another acknowledge, then issues the Word

Address Byte 0. After the device acknowledges receipt

of the Word Address Byte 0, the master issues

another start condition and the Slave Address Byte with

the R/W bit set to one. This is followed by an acknowl-

edge and then eight bits of data from the device. The

master terminates the read operation by not respond-

ing with an acknowledge and then issuing a stop con-

dition. Refer to Figure 9 for the address, acknowledge,

and data transfer sequence.

The device will perform a similar operation called “Set

Current Address” if a stop is issued instead of the sec-

ond start shown in Figure 15. The device will go into

standby mode after the stop and all bus activity will be

ignored until a start is detected. The effect of this oper-

ation is that the new address is loaded into the

address counter, but no data is output by the device.

The next Current Address Read operation will read

from the newly loaded address.

Byte Load Completed

by Issuing Stop.

Enter ACK Polling

Issue

Start

Issue Slave

Address Byte

(Read or Write)

ACK

Returned?

High

Cycle Complete.

Continue

Sequence?

Continue Normal

Read or Write

Command Sequence?

PROCEED

Issue Stop

YES

Issue Stop

Voltage

the Slave

Slave

Address

Data

Signals from

the Master

SDA Bus

Signals from

SP010 1

X45620

FN8250.0

July 29, 2005

Figure 15. Random Read Sequence

Figure 16. Sequential Read Sequence

Sequential Read

Sequential reads can be initiated as either a current

address read or random read. The first Data Byte is

transmitted as with the other modes; however, the

master now responds with an acknowledge, indicating

it requires additional data. The device continues to

output data for each acknowledge received. The master

terminates the read operation by not responding with an

acknowledge and then issuing a stop condition.

The data output is sequential, with the data from

address n followed by the data from address n + 1.

The address counter for read operations increments

through all byte addresses, allowing the entire memory

contents to be read during one operation. At the end of

the address space the counter “rolls over” to address

0000h and the device continues to output data for

each acknowledge received. Refer to Figure 16 for the

acknowledge and data transfer sequence.

CONTROL REGISTER (CR)

The Control Register is located in an area logically

separated from the array and is only accessible via a

byte write to the register address of FFFFH. The Con-

trol Register is physically part of the array.

The CR can only be modified by performing a byte write

operation directly to the address of the register and only

one data byte is allowed for each register write operation.

Prior to initiating a nonvolatile write to the CR, the WEL

and RWEL bits must be set using a two step process,

with the whole sequence requiring 3 steps.

The user must issue a stop, after sending this byte to

the register, to initiate the high voltage cycle that

writes PUP, WD1, WD0, BP1, BP0 and WPEN to the

nonvolatile bits. The part will not acknowledge any

data bytes written after the first byte is entered. A stop

must also be issued after a volatile register write oper-

ation to put the device into Standby. After a write to the

CR, the address counter contents are undefined.

The state of the CR can be read by performing a ran-

dom read at the address of the register at any time.

Only one byte is read by the register read operation.

The part will reset itself after the first byte is read. The

master should supply a stop condition to be consistent

with the bus protocol, but a stop is not required to end

this operation. After the read of the CR, the address

counter contents are reset to zero, but the user will be

told these bits are undefined and instructed to do a

random read.

Table 1. Control Register

RWEL: Register Write Enable Latch (Volatile)

The RWEL bit must be set to “1” prior to a write to

Control Register.

Signals from

the Master

SDA Bus

Signals from

the Slave

Data

S PS1010

Slave

Address

Byte 1

Word Address

Byte 0

Word Address

Slave

Address

(1)

(2) (n–1) (n)

(n is any integer greater than 1)

Signals from

the Master

SDA Bus

Signals from

the Slave

Slave

Address

Data Data Data Data

76543210

WPEN WD1 WD0 BP1 BP0 RWEL WEL PUP

X45620

FN8250.0

July 29, 2005

WEL: Write Enable Latch (Volatile)

The WEL bit controls the access to the memory and to

the Register during a write operation. This bit is a volatile

latch that powers up in the LOW (disabled) state. While

the WEL bit is LOW, writes to any address, including any

control registers will be ignored (no acknowledge will be

issued after the Data Byte). The WEL bit is set by writing

a “1” to the WEL bit and zeros to the other bits of the con-

trol register. Once set, WEL remains set until either it is

reset to 0 (by writing a “0” to the WEL bit and zeros to the

other bits of the control register) or until the part powers

up again. Writes to WEL bit do not cause a high voltage

write cycle, so the device is ready for the next operation

immediately after the stop condition.

BP1, BP0: Block Protect Bits (Nonvolatile)

The Block Protect Bits, BP1 and BP0, determine which

blocks of the array are write protected. A write to a pro-

tected block of memory is ignored. The block protect bits

will prevent write operations to one of four segments of

the array. The partitions are described in Table 2.

WD1, WD0: Watchdog Timer Bits (Nonvolatile)

The Watchdog Timer circuit monitors the micro-

processor activity by monitoring the SCL and SDA pins.

In normal operation, the microprocessor must

periodically restart the Watchdog Timer to prevent WDO

from going active. The watchdog timer is restarted on the

first HIGH to LOW transition on SCL after a start

command. The state of two nonvolatile control bits in the

Status Register determines the watchdog timer period.

The microprocessor can change these watchdog bits by

writing to the status register.

The Watchdog Timer oscillator stops when in battery

backup mode. It re-starts when V

returns.

Write Protect Enable Bit—WPEN (Nonvolatile)

The Write Protect (WP) pin and the Write Protect Enable

(WPEN) bit in the Control Register control the Program-

mable Hardware Write Protect feature. Hardware Write

Protection is enabled when the WP pin is connected to

and the WPEN bit is HIGH, and disabled when WP

pin is connected to ground. When the chip is in ROM

mode, nonvolatile writes are disabled to all non-volatile

bits in the CR, including the Block Protect bits and the

WPEN bit itself, as well as to the block protected sections

in the memory array. Only the sections of the memory

array that are not block protected can be written. Note

that since the WPEN bit is write protected, it cannot be

changed back to a LOW state; so write protection is

enabled as long as the WP pin is held connected to V

PUP: Power-on Reset (Nonvolatile)

The Power-on reset time (t

PURST

) bit, PUP, sets the

initial power-on reset time. There are two standard

settings.

Note 1. Watchdog timer is shipped disabled.

2. The t

PURST

time is set to 150ms at the factory.

Any changes to the Control Register take effect,

following either the next command (read or write) or

cycling the power to the device.

The recommended procedure for changing the

Watchdog Timer settings is to do a WREN, followed

by a write status register command. Then execute a

software loop to read the status register until an ACK

is returned (ACK polling) complete the read operation.

A valid alternative is to do a WREN, followed by a

write status register command. Then wait 10ms and

do a read status command.

Table 2. Block Protect Bits

Status Register Bit

Watchdog Time Out

(Typical)WD1 WD0

0 0 800 milliseconds

0 1 400 milliseconds

1 0 150 milliseconds

1 1 Disabled (factory setting)

PUP Time

0 150 ms (factory settings)

1 800 ms

BP1 BP0 Protected Addresses Array Lock

0 0 None None (factory setting)

0 1 6000h - 7FFFh (8K bytes) Upper 1/4 (Q4)

1 0 4000h - 7FFFh (16K bytes) Upper 1/2 (Q3, Q4)

1 1 0000h - 7FFFh (32K bytes) Full Array (All)

X45620

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

X45620V20I-2.7

Mfr. #:

Buy X45620V20I-2.7

Manufacturer:

Renesas / Intersil

Description:

IC VOLT MON DUAL SW EEPR 20TSSOP

Lifecycle:

New from this manufacturer.

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X45620V20I-2.7

X45620V20I-2.7

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