12
FN8250.0
July 29, 2005
TWO WIRE SERIAL MEMORY
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock
protection. The
array is internally organized as x 8. The device features
two wire and software protocol allowing operation on a
simple four-wire bus.
Two device select inputs (S
0
–S
1
) allow up to four
devices to share a common two wire bus.
A Control Register at the highest address location,
FFFFh, provides three write protection features: Soft-
ware Write Protect, Block Lock Protect, and Program-
mable ROM. The Software Write Protect feature
prevents any nonvolatile writes to the device until the
WEL bit in the Control Register is set. The Block Lock
Protection feature gives the user eight array block pro-
tect options, set by programming three bits in the Con-
trol Register. The Programmable ROM feature allows
the user to install the device with WP tied to V
CC
, write
to and Block Lock the desired portions of the memory
array in circuit, and then enable the In Circuit Program-
mable ROM Mode by programming the WPEN bit HIGH
in the Control Register. After this, the Block Locked por-
tions of the array, including the Control Register itself,
are protected from being erased if WP is high.
Intersil EEPROMs are designed and tested for appli-
cations requiring extended endurance. Inherent data
retention is greater than 100 years.
DETAILED PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
up resistor selection graph at the end of this data
sheet.
Device Select (S
0
, S
1
)
The device select inputs (S
0
, S
1
) are used to set bits in
the slave address. This allows up to four devices to
share a common bus. These inputs can be static or
actively driven. If used statically they must be tied to
V
SS
or V
CC
as appropriate. If actively driven, they
must be driven with CMOS levels (driven to V
CC
or
V
SS
) and they must be constant between each start
and stop issued on the SDA bus. These pins have an
active pull down internally and will be sensed as low if
the pin is left unconnected.
Write Protect (WP)
WP must be constant between each start and stop
issued on the SDA bus and is always active (not
gated). The WP pin has an active pull down to disable
the write protection when the input is left floating. The
Write Protect input controls the Hardware Write Pro-
tect feature. When held LOW, Hardware Write Protec-
tion is disabled. When this input is held HIGH, and the
WPEN bit in the Control Register is set HIGH, the
Control Register is protected, preventing changes to
the Block Lock Protection and WPEN bits.
DEVICE OPERATION
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the device will be considered a slave in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 7 and 8.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
X45620
