14
FN8250.0
July 29, 2005
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits
of the Slave Address Byte are the device type identi-
fier bits. These must equal “1010”. The next 3 bits are
the device select bits “0”, S
1
, and S
0
. This allows up to
4 devices to share a single bus. These bits are com-
pared to the S
0
, S
1
, device select input pins. The last
bit of the Slave Address Byte defines the operation to
be performed. When the R/W
bit is a one, then a read
operation is selected. When it is zero then a write
operation is selected. Refer to Figure 10. After loading
the Slave Address Byte from the SDA bus, the device
compares the device type bits with the value “1010”
and the device select bits with the status of the device
select input pins. If the compare is not successful, no
acknowledge is output during the ninth clock cycle and
the device returns to the standby mode.
On power-up the internal address is undefined, so the
first read or write operation must supply an address.
The word address is either supplied by the master or
obtained from an internal counter, depending on the
operation. The master must supply the initial two Word
Address Bytes as shown in Figure 10.
The internal organization of the E
2
array is 512 pages
by 64 bytes per page. The page address is partially
contained in the Word Address Byte 1 and partially in
bits 7 through 6 of the Word Address Byte 0. The byte
address is contained in bits 5 through 0 of the Word
Address Byte 0. See Figure 10.
WRITE OPERATIONS
Byte Write
For a write operation, the device follows “3 byte” proto-
col, consisting of one Slave Address Byte, one Word
Address Byte 1, and the Word Address Byte 0, which
gives the master access to any one of the words in the
array. Upon receipt of the Word Address Byte 0, the
device responds with an acknowledge, and waits for
the first eight bits of data. After receiving the 8 bits of
the data byte, the device again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress
the device inputs are disabled and the device will not
respond to any requests from the master. The SDA pin
is at high impedance. See Figure 11. Refer to bus tim-
ing on page 21.
Figure 10. Device Addressing
Page Write
The device is capable of a 64 byte page write operation.
It is initiated in the same manner as the byte write
operation; but instead of terminating the write operation
after the first data word is transferred, the master can
transmit up to sixty-three more words. The device will
respond with an acknowledge after the receipt of each
word, and then the byte address is internally incre-
mented by one. The page address remains constant.
When the counter reaches the end of the page, it “rolls
over” and goes back to the first byte of the current
page. This means that the master can write 64-bytes
to the page beginning at any byte. If the master begins
writing at byte 32, and loads 64-bytes, then the first
32-bytes are written to bytes 32 through 63, and the
last 16 words are written to bytes 0 through 31. After-
wards, the address counter would point to byte 32. If
the master writes more than 64 bytes, then the previ-
ously loaded data is overwritten by the new data, one
byte at a time.
1
S
1
S
0
R/W
Device
Select
010
Device Type
Identifier
Slave Address Byte
D7 D2 D1D6 D5 D4 D3
Data Byte
A2 A1 A0
A5
A4 A3
Word Address Byte 0
* A10 A9 A8A14
High Order Word Address
A11
X45620 Word Address Byte 1
A13 A12
A7 A6
D0
*This bit is 0 for access to the array and
0
Low Order Word Address
1 for access to the Control Register
X45620
