5
FN8250.0
July 29, 2005
Notes: (1) The device enters the Active state after any start, and remains active until 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or t
WC
after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any Stop, except those that initiate a high voltage write cycle; t
WC
after a stop that initiates a
high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) V
IL
min. and V
IH
max. are for reference only and are not tested.
(4) This parameter is guaranteed by characterization.
CAPACITANCE T
A
= +25°C, f = 1MHz, V
CC
= 5V
EQUIVALENT A.C. LOAD CIRCUIT AT 5V V
CC
A.C. TEST CONDITIONS
V
OLR
Output (RESET, LOWLINE, WDO,
V2FAIL
) LOW Voltage
0.4 V I
OL
= 3.0mA (5V)
I
OL
= 1.0mA (3V)
Two Wire Interface
V
IL
Input (SDA, S0, S1, SCL, WP) LOW
Voltage
-0.5 V
CC
x 0.3 V Note 3
V
IH
Input (SDA, S0, S1, SCL, WP) HIGH
Voltage
V
CC
x 0.7 V
CC
+ 0.5 V Note 3
I
LI
Input Leakage Current (SDA, S1, S0,
SCL, WP)
±10 µA
V
OLS
Output (SDA) LOW Voltage 0.4 V I
OL
= 3.0mA (5V)
I
OL
= 1.0mA (3V), Note 4
D.C. OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions unless otherwise specified)
Symbol Parameter
Limits
Unit Test ConditionsMin Typ (6) Max
Symbol Test Max Unit Conditions
C
OUT
Output Capacitance (SDA, RESET, V2FAIL, LOWLINE, BATT-ON, WDO)8pFV
OUT
= 0V,
Note 1, 4
C
IN
Input Capacitance (SDA, SCL, S0, S1, WP) 6 pF V
IN
= 0V,
Note 1, 4
V
CC
SDA
30pF
1.53kΩ
V
CC
1.53kΩ
30pF
BATT-ON
RESET
4481Ω
V2FAIL
LOWLINE
WDO
Input pulse levels V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times 10ns
Input and output timing level V
CC
x 0.5
X45620