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72V8985JG8

P1-P3P4-P6P7-P9P10-P12P13-P14
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
AUGUST 2003
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
256 x 256
IDT72V8985
DSC-5707/5
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS
is a trademark of Mitel Corp.
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
• 256 x 256 channel non-blocking switch
• Automatic signal identification (ST-BUS
®
, GCI)
• 8 RX inputs—32 channels at 64 Kbit/s per serial line
• 8 TX outputs—32 channels at 64 Kbit/s per serial line
• Three-state serial outputs
• Microprocessor Interface (8-bit data bus)
• Frame Integrity for data applications
• 3.3V Power Supply
• Available in 44-pin Plastic Leaded Chip Carrier (PLCC)
••
••
•
Operating Temperature Range -40
°°
°°
°C to +85
°°
°°
°C
••
••
• 3.3V I/O with 5V Tolerant Inputs
DESCRIPTION:
The IDT72V8985 is a ST-BUS
®
/GCI compatible digital switch controlled by
a microprocessor. The IDT72V8985 can handle as many as 256, 64 Kbit/s input
and output channels. Those 256 channels are divided into 8 serial inputs and
outputs, each of which consists of 32 channels. The IDT72V8985 provides per-
channel variable or constant throughput delay modes and microprocessor read
and write access to individual channels. As an important function of a digital
switch is to maintain sequence integrity and minimize throughput delay, the
IDT72V8985 is an ideal solution for most switching needs.
FUNCTIONAL DESCRIPTION
Frame sequence, constant throughput delay, and guaranteed minimum
delay are high priority requirements in today’s integrated data and multimedia
networks. The IDT72V8985 provides these functions on a per-channel basis
using a standard microprocessor control interface. Each of the eight serial lines
is designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data.
In Processor Mode, the microprocessor can access the input and output time
slots to control other devices such as ISDN transceivers and trunk interfaces.
Supporting both GCI and ST-BUS
®
formats, IDT72V8985 has incorporated an
internal circuit to automatically identify the polarity and format of the frame
synchronization.
A functional block diagram of the IDT72V8985 device is shown on page 1.
The serial streams operate continuously at 2.048 Mb/s and are arranged in
125µs wide frames each containing 32, 8-bit channels. Eight input (RX0-7) and
eight output (TX0-7) serial streams are provided in the IDT72V8985 device
allowing a complete 256 x 256 channel non-blocking switch matrix to be
constructed. The serial interface clock for the device is 4.096 MHz.
Microprocessor Interface
Control Register
Timing
Unit
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
ODE
F0iC4i
V
CC
CS
DS
R/W
A0/
A5
GND
CCO
DTA
D0/
D7
5707 drw01
Receive
Serial Data
Streams
Data
Memory
Output MUX
Connection
Memory
Transmit
Serial Data
Streams
RESET
(1)
NOTE:
1. The RESET Input is only provided on the SSOP package.
2
Commercial Temperature Range
IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
35
34
33
32
31
30
29
37
36
3
2
44
1
43
42
41
5
4
6
5707 drw02
INDEX
38
39
40
21
22
24
23
25
26
27
19
20
18
28
DS
CS
R/
W
11
12
13
14
15
16
17
9
10
8
7
RX2
RX1
RX0
DTA
TX0
TX1
TX2
DNC
(1)
CCO
ODE
TX3
TX4
TX5
TX6
TX7
GND
D
0
RX3
RX4
RX5
RX6
RX7
V
CC
F0i
C4i
A
0
D1
D2
D3
D4
A
1
A
2
DNC
(1)
DNC
(1)
DNC
(1)
D5
D6
D7
A5
A4
A3
PIN CONFIGURATION
PLCC: 0.05in. pitch, 0.65in. x 0.65in
(J44-1, order code: J)
TOP VIEW
TOP VIEW
DTA
CCO
ODE
1
2
40
39
TX0
3
38
TX1
4
37
TX2
5
36
TX3
6
35
TX4
7
34
TX5
8
33
TX6
9
32
TX7
10
31
GND
11
30
12
29
CS
13
28
14
27
15
16
17
18
19
20
26
25
RX1
RX2
RX3
RX4
RX5
RX6
F0i
R/W
DS
C4i
V
CC
RX7
RX0
21
22
23
2
4
48
47
46
45
44
43
42
41
GND
RESET
(2)
GND
5707 drw04
DNC
(1)
A
0
D0
DNC
(1)
DNC
(1)
DNC
(1)
V
CC
D1
D2
D3
D4
D5
D6
D7
A
1
A
2
A
3
A
5
A
4
NOTES:
1. DNC - Do Not Connect
2. The RESET Input is only provided on the SSOP package.
PQFP: 0.80mm pitch, 10mm x 10mm
(DB44-1, order code: DB)
TOP VIEW
29
28
27
26
25
24
23
31
30
44
43
42
41
5707 drw03
INDEX
32
33
40
DS
CS
R/
W
5
6
7
8
9
10
11
3
4
2
1
RX2
RX1
RX0
DTA
TX0
TX1
TX2
DNC
(1)
CCO
ODE
TX3
TX4
TX5
TX6
TX7
GND
D
0
RX3
RX4
RX5
RX6
RX7
V
CC
F0i
C4i
A
0
D
1
D
2
D
3
D
4
A
1
A
2
DNC(1)
DNC
(1)
DNC
(1)
D
5
D
6
D
7
A
5
A
4
A
3
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
Package Type Reference Identifier Order Code
SSOP: 0.025in. pitch, 0.625in. x 0.295in. SO48-1 PV
3
Commercial Temperature Range
IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
PIN DESCRIPTIONS
SYMBOL NAME I/O DESCRIPTION
GND Ground. Ground Rail.
V
CC VCC +3.3 Volt Power Supply.
DTA Data Acknowledgment O This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this
(Open Drain) output.
RX0-7 RX Input 0 to 7 I Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s.
F0i Frame Pulse I This input accepts and automatically identifies frame synchronization signals formatted according to different
backplane specifications such as ST-BUS
®
and GCI.
C4i Clock I 4.096 MHz serial clock for shifting data in and out of the data streams.
A0-A5 Address 0 to 5 I These lines provide the address to IDT72V8985 internal registers.
DS Data Strobe I This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with
CS to enable the internal read and write generation.
R/W Read/Write I This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.
CS Chip Select I Active LOW input enabling a microprocessor read or write of control register or internal memories.
D0-D7 Data Bus 0 to 7 I/O These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH,
Connection Memory LOW and data memory.
TX0-7 TX Outputs 0 to 7 O Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s.
(Three-state Outputs)
ODE Output Drive Enable I This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. If this is
HIGH, each channel may still be put into high-impedance by software control.
CCO Control Channel Output O This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the
contents of the CCO bit in the Connection Memory HIGH locations.
RESET Device Reset I This input (active LOW) puts the IDT72V8985 in its reset state that clears the device internal counters,
(Schmitt Trigger Input) registers and brings TX0-7 and microport data outputs to a high-impedance state. The time constant for a
power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation,
the RESET pin must be held LOW for a minimum of 100ns to reset the device.
P1-P3P4-P6P7-P9P10-P12P13-P14

72V8985JG8

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Buy 72V8985JG8
Manufacturer:
IDT
Description:
Digital Bus Switch ICs 3.3V 256 X 256 TSI SWITCH
Lifecycle:
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